techlibs/xilinx/abc_xc7.box

   1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
   2 #                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
   3
   4 # NB: Inputs/Outputs must be ordered alphabetically
   5 #     (with exceptions for carry in/out)
   6
   7 # Average across F7[AB]MUX
   8 # Inputs: I0 I1 S0
   9 # Outputs: O
  10 F7MUX 1 1 3 1
  11 204 208 286
  12
  13 # Inputs: I0 I1 S0
  14 # Outputs: O
  15 MUXF8 2 1 3 1
  16 104 94 273
  17
  18 # Box containing MUXF7.[AB] + MUXF8
  19 # Inputs: I0 I1 I2 I3 S0 S1
  20 # Outputs: O
  21 $__MUXF78 3 1 6 1
  22 294 297 311 317 390 273
  23
  24 # CARRY4 + CARRY4_[ABCD]X
  25 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
  26 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
  27 #   (NB: carry chain input/output must be last
  28 #        input/output and the entire bus has been
  29 #        moved there overriding the otherwise
  30 #        alphabetical ordering)
  31 CARRY4 4 1 10 8
  32 482 -   -   -   -   223 -   -   -   222
  33 598 407 -   -   -   400 205 -   -   334
  34 584 556 537 -   -   523 558 226 -   239
  35 642 615 596 438 -   582 618 330 227 313
  36 536 379 -   -   -   340 -   -   -   271
  37 494 465 445 -   -   433 469 -   -   157
  38 592 540 520 356 -   512 548 292 -   228
  39 580 526 507 398 385 508 528 378 380 114
  40
  41 # SLICEM/A6LUT
  42 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
  43 # Outputs: DPO SPO
  44 RAM32X1D 5 0 13 2
  45 -   -   -   -   -   - 631 472 407 238 127 - -
  46 631 472 407 238 127 - -   -   -   -   -   - -
  47
  48 # SLICEM/A6LUT
  49 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
  50 # Outputs: DPO SPO
  51 RAM64X1D 6 0 15 2
  52 -   -   -   -   -   -   - 642 631 472 407 238 127 - -
  53 642 631 472 407 238 127 - -   -   -   -   -   -   - -
  54
  55 # SLICEM/A6LUT + F7[AB]MUX
  56 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
  57 # Outputs: DPO SPO
  58 RAM128X1D 7 0 17 2
  59 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
  60 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
  61
  62 # Box to emulate async behaviour of FD[CP]*
  63 # Inputs: A S
  64 # Outputs: Y
  65 $__ABC_ASYNC 1000 0 2 1
  66 0 764
  67
  68 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
  69 # reflect the -46ps Tsu
  70 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
  71 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
  72
  73 # Inputs: C CE D R \$pastQ
  74 # Outputs: Q
  75 FDRE 1001 1 5 1
  76 0 151 0 446 0
  77
  78 # Inputs: C CE D R \$pastQ
  79 # Outputs: Q
  80 FDRE_1 1002 1 5 1
  81 0 151 0 446 0
  82
  83 # Inputs: C CE CLR D \$pastQ
  84 # Outputs: Q
  85 FDCE 1003 1 5 1
  86 0 151 806 0 0
  87
  88 # Inputs: C CE CLR D \$pastQ
  89 # Outputs: Q
  90 FDCE_1 1004 1 5 1
  91 0 151 806 0 0
  92
  93 # Inputs: C CE D PRE \$pastQ
  94 # Outputs: Q
  95 FDPE 1005 1 5 1
  96 0 151 0 806 0
  97
  98 # Inputs: C CE D PRE \$pastQ
  99 # Outputs: Q
 100 FDPE_1 1006 1 5 1
 101 0 151 0 806 0