techlibs/xilinx/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // LCU
  22
  23 (* techmap_celltype = "$lcu" *)
  24 module _80_xilinx_lcu (P, G, CI, CO);
  25         parameter WIDTH = 2;
  26
  27         input [WIDTH-1:0] P, G;
  28         input CI;
  29
  30         output [WIDTH-1:0] CO;
  31
  32         wire _TECHMAP_FAIL_ = WIDTH <= 2;
  33
  34         genvar i;
  35
  36 `ifdef _CLB_CARRY
  37
  38         localparam CARRY4_COUNT = (WIDTH + 3) / 4;
  39         localparam MAX_WIDTH    = CARRY4_COUNT * 4;
  40         localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;
  41
  42         wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, P & ~G};
  43         wire [MAX_WIDTH-1:0] C  = CO;
  44
  45         generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
  46
  47                 // Partially occupied CARRY4
  48                 if ((i+1)*4 > WIDTH) begin
  49
  50                         // First one
  51                         if (i == 0) begin
  52                                 CARRY4 carry4_1st_part
  53                                 (
  54                                 .CYINIT(CI),
  55                                 .CI    (1'd0),
  56                                 .DI    (G [(Y_WIDTH - 1):i*4]),
  57                                 .S     (S [(Y_WIDTH - 1):i*4]),
  58                                 .CO    (CO[(Y_WIDTH - 1):i*4]),
  59                                 );
  60                         // Another one
  61                         end else begin
  62                                 CARRY4 carry4_part
  63                                 (
  64                                 .CYINIT(1'd0),
  65                                 .CI    (C [i*4 - 1]),
  66                                 .DI    (G [(Y_WIDTH - 1):i*4]),
  67                                 .S     (S [(Y_WIDTH - 1):i*4]),
  68                                 .CO    (CO[(Y_WIDTH - 1):i*4]),
  69                                 );
  70                         end
  71
  72                 // Fully occupied CARRY4
  73                 end else begin
  74
  75                         // First one
  76                         if (i == 0) begin
  77                                 CARRY4 carry4_1st_full
  78                                 (
  79                                 .CYINIT(CI),
  80                                 .CI    (1'd0),
  81                                 .DI    (G [((i+1)*4 - 1):i*4]),
  82                                 .S     (S [((i+1)*4 - 1):i*4]),
  83                                 .CO    (CO[((i+1)*4 - 1):i*4]),
  84                                 );
  85                         // Another one
  86                         end else begin
  87                                 CARRY4 carry4_full
  88                                 (
  89                                 .CYINIT(1'd0),
  90                                 .CI    (C [i*4 - 1]),
  91                                 .DI    (G [((i+1)*4 - 1):i*4]),
  92                                 .S     (S [((i+1)*4 - 1):i*4]),
  93                                 .CO    (CO[((i+1)*4 - 1):i*4]),
  94                                 );
  95                         end
  96
  97                 end
  98
  99         end endgenerate
 100
 101 `elsif _EXPLICIT_CARRY
 102
 103         wire [WIDTH-1:0] C = {CO, CI};
 104         wire [WIDTH-1:0] S = P & ~G;
 105
 106         generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
 107                 MUXCY muxcy (
 108                         .CI(C[i]),
 109                         .DI(G[i]),
 110                         .S(S[i]),
 111                         .O(CO[i])
 112                 );
 113         end endgenerate
 114
 115 `else
 116
 117         wire [WIDTH-1:0] C = {CO, CI};
 118         wire [WIDTH-1:0] S = P & ~G;
 119
 120         generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
 121                 MUXCY muxcy (
 122                         .CI(C[i]),
 123                         .DI(G[i]),
 124                         .S(S[i]),
 125                         .O(CO[i])
 126                 );
 127         end endgenerate
 128 `endif
 129
 130 endmodule
 131
 132
 133 // ============================================================================
 134 // ALU
 135
 136 (* techmap_celltype = "$alu" *)
 137 module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 138         parameter A_SIGNED = 0;
 139         parameter B_SIGNED = 0;
 140         parameter A_WIDTH = 1;
 141         parameter B_WIDTH = 1;
 142         parameter Y_WIDTH = 1;
 143         parameter _TECHMAP_CONSTVAL_CI_ = 0;
 144         parameter _TECHMAP_CONSTMSK_CI_ = 0;
 145
 146         input [A_WIDTH-1:0] A;
 147         input [B_WIDTH-1:0] B;
 148         output [Y_WIDTH-1:0] X, Y;
 149
 150         input CI, BI;
 151         output [Y_WIDTH-1:0] CO;
 152
 153         wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 154
 155         wire [Y_WIDTH-1:0] A_buf, B_buf;
 156         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 157         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 158
 159         wire [Y_WIDTH-1:0] AA = A_buf;
 160         wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 161
 162         genvar i;
 163
 164 `ifdef _CLB_CARRY
 165
 166         localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
 167         localparam MAX_WIDTH    = CARRY4_COUNT * 4;
 168         localparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;
 169
 170         wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};
 171         wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
 172
 173         wire [MAX_WIDTH-1:0] C  = CO;
 174
 175         genvar i;
 176         generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
 177
 178                 // Partially occupied CARRY4
 179                 if ((i+1)*4 > Y_WIDTH) begin
 180
 181                         // First one
 182                         if (i == 0) begin
 183                                 CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part
 184                                 (
 185                                 .CYINIT(CI),
 186                                 .CI    (1'd0),
 187                                 .DI    (DI[(Y_WIDTH - 1):i*4]),
 188                                 .S     (S [(Y_WIDTH - 1):i*4]),
 189                                 .O     (Y [(Y_WIDTH - 1):i*4]),
 190                                 .CO    (CO[(Y_WIDTH - 1):i*4])
 191                                 );
 192                         // Another one
 193                         end else begin
 194                                 CARRY4 carry4_part
 195                                 (
 196                                 .CYINIT(1'd0),
 197                                 .CI    (C [i*4 - 1]),
 198                                 .DI    (DI[(Y_WIDTH - 1):i*4]),
 199                                 .S     (S [(Y_WIDTH - 1):i*4]),
 200                                 .O     (Y [(Y_WIDTH - 1):i*4]),
 201                                 .CO    (CO[(Y_WIDTH - 1):i*4])
 202                                 );
 203                         end
 204
 205                 // Fully occupied CARRY4
 206                 end else begin
 207
 208                         // First one
 209                         if (i == 0) begin
 210                                 CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full
 211                                 (
 212                                 .CYINIT(CI),
 213                                 .CI    (1'd0),
 214                                 .DI    (DI[((i+1)*4 - 1):i*4]),
 215                                 .S     (S [((i+1)*4 - 1):i*4]),
 216                                 .O     (Y [((i+1)*4 - 1):i*4]),
 217                                 .CO    (CO[((i+1)*4 - 1):i*4])
 218                                 );
 219                         // Another one
 220                         end else begin
 221                                 CARRY4 carry4_full
 222                                 (
 223                                 .CYINIT(1'd0),
 224                                 .CI    (C [i*4 - 1]),
 225                                 .DI    (DI[((i+1)*4 - 1):i*4]),
 226                                 .S     (S [((i+1)*4 - 1):i*4]),
 227                                 .O     (Y [((i+1)*4 - 1):i*4]),
 228                                 .CO    (CO[((i+1)*4 - 1):i*4])
 229                                 );
 230                         end
 231
 232                 end
 233
 234         end endgenerate
 235
 236 `elsif _EXPLICIT_CARRY
 237
 238         wire [Y_WIDTH-1:0] S = AA ^ BB;
 239         wire [Y_WIDTH-1:0] DI = AA & BB;
 240
 241         wire CINIT;
 242         // Carry chain.
 243         //
 244         // VPR requires that the carry chain never hit the fabric.      The CO input
 245         // to this techmap is the carry outputs for synthesis, e.g. might hit the
 246         // fabric.
 247         //
 248         // So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
 249         // e.g. off fabric dedicated chain.  CO is the carry outputs that are
 250         // available to the fabric.
 251         wire [Y_WIDTH-1:0] CO_CHAIN;
 252         wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
 253
 254         // If carry chain is being initialized to a constant, techmap the constant
 255         // source.      Otherwise techmap the fabric source.
 256         generate for (i = 0; i < 1; i = i + 1) begin:slice
 257                 CARRY0 #(.CYINIT_FABRIC(1)) carry(
 258                         .CI_INIT(CI),
 259                         .DI(DI[0]),
 260                         .S(S[0]),
 261                         .CO_CHAIN(CO_CHAIN[0]),
 262                         .CO_FABRIC(CO[0]),
 263                         .O(Y[0])
 264                 );
 265         end endgenerate
 266
 267         generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
 268                 if(i % 4 == 0) begin
 269                         CARRY0 carry (
 270                                 .CI(C[i]),
 271                                 .DI(DI[i]),
 272                                 .S(S[i]),
 273                                 .CO_CHAIN(CO_CHAIN[i]),
 274                                 .CO_FABRIC(CO[i]),
 275                                 .O(Y[i])
 276                         );
 277                 end
 278                 else
 279                 begin
 280                         CARRY carry (
 281                                 .CI(C[i]),
 282                                 .DI(DI[i]),
 283                                 .S(S[i]),
 284                                 .CO_CHAIN(CO_CHAIN[i]),
 285                                 .CO_FABRIC(CO[i]),
 286                                 .O(Y[i])
 287                         );
 288                 end
 289         end endgenerate
 290
 291         generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
 292                 if(i % 4 == 0) begin
 293                         CARRY0 top_of_carry (
 294                                 .CI(C[i]),
 295                                 .DI(DI[i]),
 296                                 .S(S[i]),
 297                                 .CO_CHAIN(CO_CHAIN[i]),
 298                                 .O(Y[i])
 299                         );
 300                 end
 301                 else
 302                 begin
 303                         CARRY top_of_carry (
 304                                 .CI(C[i]),
 305                                 .DI(DI[i]),
 306                                 .S(S[i]),
 307                                 .CO_CHAIN(CO_CHAIN[i]),
 308                                 .O(Y[i])
 309                         );
 310                 end
 311                 // Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
 312                 // a non-congested path to output the top of the carry chain.
 313                 // Registering the output of the CARRY block would solve this, but not
 314                 // all designs do that.
 315                 if((i+1) % 4 == 0) begin
 316                         CARRY0 carry_output (
 317                                 .CI(CO_CHAIN[i]),
 318                                 .DI(0),
 319                                 .S(0),
 320                                 .O(CO[i])
 321                         );
 322                 end
 323                 else
 324                 begin
 325                         CARRY carry_output (
 326                                 .CI(CO_CHAIN[i]),
 327                                 .DI(0),
 328                                 .S(0),
 329                                 .O(CO[i])
 330                         );
 331                 end
 332         end endgenerate
 333
 334 `else
 335
 336         wire [Y_WIDTH-1:0] S = AA ^ BB;
 337         wire [Y_WIDTH-1:0] DI = AA & BB;
 338
 339         wire [Y_WIDTH-1:0] C = {CO, CI};
 340
 341         generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 342                 MUXCY muxcy (
 343                         .CI(C[i]),
 344                         .DI(DI[i]),
 345                         .S(S[i]),
 346                         .O(CO[i])
 347                 );
 348                 XORCY xorcy (
 349                         .CI(C[i]),
 350                         .LI(S[i]),
 351                         .O(Y[i])
 352                 );
 353         end endgenerate
 354
 355 `endif
 356
 357         assign X = S;
 358 endmodule
 359