techlibs/xilinx/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // LCU
  22
  23 (* techmap_celltype = "$lcu" *)
  24 module _80_xilinx_lcu (P, G, CI, CO);
  25         parameter WIDTH = 2;
  26
  27         (* force_downto *)
  28         input [WIDTH-1:0] P, G;
  29         input CI;
  30
  31         (* force_downto *)
  32         output [WIDTH-1:0] CO;
  33
  34         wire _TECHMAP_FAIL_ = WIDTH <= 2;
  35
  36         genvar i;
  37
  38 `ifdef _EXPLICIT_CARRY
  39         localparam EXPLICIT_CARRY = 1'b1;
  40 `else
  41         localparam EXPLICIT_CARRY = 1'b0;
  42 `endif
  43
  44 generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
  45
  46         (* force_downto *)
  47         wire [WIDTH-1:0] C = {CO, CI};
  48         (* force_downto *)
  49         wire [WIDTH-1:0] S = P & ~G;
  50
  51         generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
  52                 MUXCY muxcy (
  53                         .CI(C[i]),
  54                         .DI(G[i]),
  55                         .S(S[i]),
  56                         .O(CO[i])
  57                 );
  58         end endgenerate
  59
  60 end else begin
  61
  62         localparam CARRY4_COUNT = (WIDTH + 3) / 4;
  63         localparam MAX_WIDTH    = CARRY4_COUNT * 4;
  64         localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;
  65
  66         (* force_downto *)
  67         wire [MAX_WIDTH-1:0] S =  {{PAD_WIDTH{1'b0}}, P & ~G};
  68         (* force_downto *)
  69         wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
  70         (* force_downto *)
  71         wire [MAX_WIDTH-1:0] C;
  72         assign CO = C;
  73
  74         generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
  75                 if (i == 0) begin
  76                         CARRY4 carry4
  77                         (
  78                         .CYINIT(CI),
  79                         .CI    (1'd0),
  80                         .DI    (GG[i*4 +: 4]),
  81                         .S     (S [i*4 +: 4]),
  82                         .CO    (C [i*4 +: 4]),
  83                         );
  84                 end else begin
  85                         CARRY4 carry4
  86                         (
  87                         .CYINIT(1'd0),
  88                         .CI    (C [i*4 - 1]),
  89                         .DI    (GG[i*4 +: 4]),
  90                         .S     (S [i*4 +: 4]),
  91                         .CO    (C [i*4 +: 4]),
  92                         );
  93                 end
  94         end endgenerate
  95 end endgenerate
  96
  97 endmodule
  98
  99
 100 // ============================================================================
 101 // ALU
 102
 103 (* techmap_celltype = "$alu" *)
 104 module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 105         parameter A_SIGNED = 0;
 106         parameter B_SIGNED = 0;
 107         parameter A_WIDTH = 1;
 108         parameter B_WIDTH = 1;
 109         parameter Y_WIDTH = 1;
 110         parameter _TECHMAP_CONSTVAL_CI_ = 0;
 111         parameter _TECHMAP_CONSTMSK_CI_ = 0;
 112
 113         (* force_downto *)
 114         input [A_WIDTH-1:0] A;
 115         (* force_downto *)
 116         input [B_WIDTH-1:0] B;
 117         (* force_downto *)
 118         output [Y_WIDTH-1:0] X, Y;
 119
 120         input CI, BI;
 121         (* force_downto *)
 122         output [Y_WIDTH-1:0] CO;
 123
 124         wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 125
 126         (* force_downto *)
 127         wire [Y_WIDTH-1:0] A_buf, B_buf;
 128         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 129         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 130
 131         (* force_downto *)
 132         wire [Y_WIDTH-1:0] AA = A_buf;
 133         (* force_downto *)
 134         wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 135
 136         genvar i;
 137
 138 `ifdef _EXPLICIT_CARRY
 139         localparam EXPLICIT_CARRY = 1'b1;
 140 `else
 141         localparam EXPLICIT_CARRY = 1'b0;
 142 `endif
 143
 144 generate if (`LUT_SIZE == 4) begin
 145
 146         (* force_downto *)
 147         wire [Y_WIDTH-1:0] C = {CO, CI};
 148         (* force_downto *)
 149         wire [Y_WIDTH-1:0] S  = {AA ^ BB};
 150
 151         genvar i;
 152         generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 153                 MUXCY muxcy (
 154                         .CI(C[i]),
 155                         .DI(AA[i]),
 156                         .S(S[i]),
 157                         .O(CO[i])
 158                 );
 159                 XORCY xorcy (
 160                         .CI(C[i]),
 161                         .LI(S[i]),
 162                         .O(Y[i])
 163                 );
 164         end endgenerate
 165
 166 end else if (EXPLICIT_CARRY) begin
 167
 168         (* force_downto *)
 169         wire [Y_WIDTH-1:0] S = AA ^ BB;
 170
 171         wire CINIT;
 172         // Carry chain.
 173         //
 174         // VPR requires that the carry chain never hit the fabric.      The CO input
 175         // to this techmap is the carry outputs for synthesis, e.g. might hit the
 176         // fabric.
 177         //
 178         // So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
 179         // e.g. off fabric dedicated chain.  CO is the carry outputs that are
 180         // available to the fabric.
 181         (* force_downto *)
 182         wire [Y_WIDTH-1:0] CO_CHAIN;
 183         (* force_downto *)
 184         wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
 185
 186         // If carry chain is being initialized to a constant, techmap the constant
 187         // source.      Otherwise techmap the fabric source.
 188         generate for (i = 0; i < 1; i = i + 1) begin:slice
 189                 CARRY0 #(.CYINIT_FABRIC(1)) carry(
 190                         .CI_INIT(CI),
 191                         .DI(AA[0]),
 192                         .S(S[0]),
 193                         .CO_CHAIN(CO_CHAIN[0]),
 194                         .CO_FABRIC(CO[0]),
 195                         .O(Y[0])
 196                 );
 197         end endgenerate
 198
 199         generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
 200                 if(i % 4 == 0) begin
 201                         CARRY0 carry (
 202                                 .CI(C[i]),
 203                                 .DI(AA[i]),
 204                                 .S(S[i]),
 205                                 .CO_CHAIN(CO_CHAIN[i]),
 206                                 .CO_FABRIC(CO[i]),
 207                                 .O(Y[i])
 208                         );
 209                 end
 210                 else
 211                 begin
 212                         CARRY carry (
 213                                 .CI(C[i]),
 214                                 .DI(AA[i]),
 215                                 .S(S[i]),
 216                                 .CO_CHAIN(CO_CHAIN[i]),
 217                                 .CO_FABRIC(CO[i]),
 218                                 .O(Y[i])
 219                         );
 220                 end
 221         end endgenerate
 222
 223         generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
 224                 if(i % 4 == 0) begin
 225                         CARRY0 top_of_carry (
 226                                 .CI(C[i]),
 227                                 .DI(AA[i]),
 228                                 .S(S[i]),
 229                                 .CO_CHAIN(CO_CHAIN[i]),
 230                                 .O(Y[i])
 231                         );
 232                 end
 233                 else
 234                 begin
 235                         CARRY top_of_carry (
 236                                 .CI(C[i]),
 237                                 .DI(AA[i]),
 238                                 .S(S[i]),
 239                                 .CO_CHAIN(CO_CHAIN[i]),
 240                                 .O(Y[i])
 241                         );
 242                 end
 243                 // Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
 244                 // a non-congested path to output the top of the carry chain.
 245                 // Registering the output of the CARRY block would solve this, but not
 246                 // all designs do that.
 247                 if((i+1) % 4 == 0) begin
 248                         CARRY0 carry_output (
 249                                 .CI(CO_CHAIN[i]),
 250                                 .DI(0),
 251                                 .S(0),
 252                                 .O(CO[i])
 253                         );
 254                 end
 255                 else
 256                 begin
 257                         CARRY carry_output (
 258                                 .CI(CO_CHAIN[i]),
 259                                 .DI(0),
 260                                 .S(0),
 261                                 .O(CO[i])
 262                         );
 263                 end
 264         end endgenerate
 265
 266 end else begin
 267
 268         localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
 269         localparam MAX_WIDTH    = CARRY4_COUNT * 4;
 270         localparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;
 271
 272         (* force_downto *)
 273         wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};
 274         (* force_downto *)
 275         wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
 276
 277         (* force_downto *)
 278         wire [MAX_WIDTH-1:0] O;
 279         (* force_downto *)
 280         wire [MAX_WIDTH-1:0] C;
 281         assign Y = O, CO = C;
 282
 283         genvar i;
 284         generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
 285                 if (i == 0) begin
 286                         CARRY4 carry4
 287                         (
 288                         .CYINIT(CI),
 289                         .CI    (1'd0),
 290                         .DI    (DI[i*4 +: 4]),
 291                         .S     (S [i*4 +: 4]),
 292                         .O     (O [i*4 +: 4]),
 293                         .CO    (C [i*4 +: 4])
 294                         );
 295                 end else begin
 296                     CARRY4 carry4
 297                     (
 298                         .CYINIT(1'd0),
 299                         .CI    (C [i*4 - 1]),
 300                         .DI    (DI[i*4 +: 4]),
 301                         .S     (S [i*4 +: 4]),
 302                         .O     (O [i*4 +: 4]),
 303                         .CO    (C [i*4 +: 4])
 304                     );
 305                 end
 306         end endgenerate
 307
 308 end endgenerate
 309
 310         assign X = S;
 311 endmodule
 312