2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
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10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // ============================================================================
23 (* techmap_celltype = "$lcu" *)
24 module _80_xilinx_lcu (P, G, CI, CO);
27 input [WIDTH-1:0] P, G;
30 output [WIDTH-1:0] CO;
32 wire _TECHMAP_FAIL_ = WIDTH <= 2;
38 localparam CARRY4_COUNT = (WIDTH + 3) / 4;
39 localparam MAX_WIDTH = CARRY4_COUNT * 4;
40 localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
42 wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
43 wire [MAX_WIDTH-1:0] C = CO;
45 generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
47 // Partially occupied CARRY4
48 if ((i+1)*4 > WIDTH) begin
52 CARRY4 carry4_1st_part
56 .DI (G [(Y_WIDTH - 1):i*4]),
57 .S (S [(Y_WIDTH - 1):i*4]),
58 .CO (CO[(Y_WIDTH - 1):i*4]),
66 .DI (G [(Y_WIDTH - 1):i*4]),
67 .S (S [(Y_WIDTH - 1):i*4]),
68 .CO (CO[(Y_WIDTH - 1):i*4]),
72 // Fully occupied CARRY4
77 CARRY4 carry4_1st_full
81 .DI (G [((i+1)*4 - 1):i*4]),
82 .S (S [((i+1)*4 - 1):i*4]),
83 .CO (CO[((i+1)*4 - 1):i*4]),
91 .DI (G [((i+1)*4 - 1):i*4]),
92 .S (S [((i+1)*4 - 1):i*4]),
93 .CO (CO[((i+1)*4 - 1):i*4]),
101 `elsif _EXPLICIT_CARRY
103 wire [WIDTH-1:0] C = {CO, CI};
104 wire [WIDTH-1:0] S = P & ~G;
106 generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
117 wire [WIDTH-1:0] C = {CO, CI};
118 wire [WIDTH-1:0] S = P & ~G;
120 generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
133 // ============================================================================
136 (* techmap_celltype = "$alu" *)
137 module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
138 parameter A_SIGNED = 0;
139 parameter B_SIGNED = 0;
140 parameter A_WIDTH = 1;
141 parameter B_WIDTH = 1;
142 parameter Y_WIDTH = 1;
143 parameter _TECHMAP_CONSTVAL_CI_ = 0;
144 parameter _TECHMAP_CONSTMSK_CI_ = 0;
146 input [A_WIDTH-1:0] A;
147 input [B_WIDTH-1:0] B;
148 output [Y_WIDTH-1:0] X, Y;
151 output [Y_WIDTH-1:0] CO;
153 wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
155 wire [Y_WIDTH-1:0] A_buf, B_buf;
156 \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
157 \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
159 wire [Y_WIDTH-1:0] AA = A_buf;
160 wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
166 localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
167 localparam MAX_WIDTH = CARRY4_COUNT * 4;
168 localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
170 wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
171 wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
173 wire [MAX_WIDTH-1:0] C = CO;
176 generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
178 // Partially occupied CARRY4
179 if ((i+1)*4 > Y_WIDTH) begin
183 CARRY4 carry4_1st_part
187 .DI (DI[(Y_WIDTH - 1):i*4]),
188 .S (S [(Y_WIDTH - 1):i*4]),
189 .O (Y [(Y_WIDTH - 1):i*4]),
190 .CO (CO[(Y_WIDTH - 1):i*4])
198 .DI (DI[(Y_WIDTH - 1):i*4]),
199 .S (S [(Y_WIDTH - 1):i*4]),
200 .O (Y [(Y_WIDTH - 1):i*4]),
201 .CO (CO[(Y_WIDTH - 1):i*4])
205 // Fully occupied CARRY4
210 CARRY4 carry4_1st_full
214 .DI (DI[((i+1)*4 - 1):i*4]),
215 .S (S [((i+1)*4 - 1):i*4]),
216 .O (Y [((i+1)*4 - 1):i*4]),
217 .CO (CO[((i+1)*4 - 1):i*4])
225 .DI (DI[((i+1)*4 - 1):i*4]),
226 .S (S [((i+1)*4 - 1):i*4]),
227 .O (Y [((i+1)*4 - 1):i*4]),
228 .CO (CO[((i+1)*4 - 1):i*4])
236 `elsif _EXPLICIT_CARRY
238 wire [Y_WIDTH-1:0] S = AA ^ BB;
239 wire [Y_WIDTH-1:0] DI = AA & BB;
244 // VPR requires that the carry chain never hit the fabric. The CO input
245 // to this techmap is the carry outputs for synthesis, e.g. might hit the
248 // So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
249 // e.g. off fabric dedicated chain. CO is the carry outputs that are
250 // available to the fabric.
251 wire [Y_WIDTH-1:0] CO_CHAIN;
252 wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
254 // If carry chain is being initialized to a constant, techmap the constant
255 // source. Otherwise techmap the fabric source.
256 generate for (i = 0; i < 1; i = i + 1) begin:slice
257 CARRY0 #(.CYINIT_FABRIC(1)) carry(
261 .CO_CHAIN(CO_CHAIN[0]),
267 generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
273 .CO_CHAIN(CO_CHAIN[i]),
284 .CO_CHAIN(CO_CHAIN[i]),
291 generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
293 CARRY0 top_of_carry (
297 .CO_CHAIN(CO_CHAIN[i]),
307 .CO_CHAIN(CO_CHAIN[i]),
311 // Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
312 // a non-congested path to output the top of the carry chain.
313 // Registering the output of the CARRY block would solve this, but not
314 // all designs do that.
315 if((i+1) % 4 == 0) begin
316 CARRY0 carry_output (
336 wire [Y_WIDTH-1:0] S = AA ^ BB;
337 wire [Y_WIDTH-1:0] DI = AA & BB;
339 wire [Y_WIDTH-1:0] C = {CO, CI};
341 generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice