Merge branch 'xaig' into xc7mux
[yosys.git] / techlibs / xilinx / cells_box.v
1 (* abc_box_id = 1 *)
2 module MUXF7(output O, input I0, I1, S);
3 assign O = S ? I1 : I0;
4 endmodule
5
6 (* abc_box_id = 2 *)
7 module MUXF8(output O, input I0, I1, S);
8 assign O = S ? I1 : I0;
9 endmodule
10