techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // Convert negative-polarity reset to positive-polarity
  21 module  \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  22 module  \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  23
  24 module  \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  25 module  \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  26
  27
  28 module \$__SHREG_ (input C, input D, input E, output Q);
  29   parameter DEPTH = 0;
  30   parameter [DEPTH-1:0] INIT = 0;
  31   parameter CLKPOL = 1;
  32   parameter ENPOL = 2;
  33
  34   \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
  35 endmodule
  36
  37 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
  38   parameter DEPTH = 0;
  39   parameter [DEPTH-1:0] INIT = 0;
  40   parameter CLKPOL = 1;
  41   parameter ENPOL = 2;
  42
  43   // shregmap's INIT parameter shifts out LSB first;
  44   // however Xilinx expects MSB first
  45   function [DEPTH-1:0] brev;
  46     input [DEPTH-1:0] din;
  47     integer i;
  48     begin
  49       for (i = 0; i < DEPTH; i=i+1)
  50         brev[i] = din[DEPTH-1-i];
  51     end
  52   endfunction
  53   localparam [DEPTH-1:0] INIT_R = brev(INIT);
  54
  55   parameter _TECHMAP_CONSTMSK_L_ = 0;
  56   parameter _TECHMAP_CONSTVAL_L_ = 0;
  57
  58   wire CE;
  59   generate
  60     if (ENPOL == 0)
  61       assign CE = ~E;
  62     else if (ENPOL == 1)
  63       assign CE = E;
  64     else
  65       assign CE = 1'b1;
  66     if (DEPTH == 1) begin
  67       if (CLKPOL)
  68           FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  69       else
  70           FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  71     end else
  72     if (DEPTH <= 16) begin
  73       SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  74     end else
  75     if (DEPTH > 17 && DEPTH <= 32) begin
  76       SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  77     end else
  78     if (DEPTH > 33 && DEPTH <= 64) begin
  79       wire T0, T1, T2;
  80       SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
  81       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
  82       if (&_TECHMAP_CONSTMSK_L_)
  83         assign Q = T2;
  84       else
  85         MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
  86     end else
  87     if (DEPTH > 65 && DEPTH <= 96) begin
  88       wire T0, T1, T2, T3, T4, T5, T6;
  89       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  90       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  91       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
  92       if (&_TECHMAP_CONSTMSK_L_)
  93         assign Q = T4;
  94       else begin
  95         MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
  96         MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
  97         MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
  98       end
  99     end else
 100     if (DEPTH > 97 && DEPTH < 128) begin
 101       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
 102       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 103       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 104       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 105       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
 106       if (&_TECHMAP_CONSTMSK_L_)
 107         assign Q = T6;
 108       else begin
 109         MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
 110         MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
 111         MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
 112       end
 113     end
 114     else if (DEPTH == 128) begin
 115       wire T0, T1, T2, T3, T4, T5, T6;
 116       SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 117       SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 118       SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 119       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
 120       if (&_TECHMAP_CONSTMSK_L_)
 121         assign Q = T6;
 122       else begin
 123         wire T7, T8;
 124         MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
 125         MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
 126         MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
 127       end
 128     end
 129     else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
 130       // Handle cases where fixed-length depth is
 131       // just 1 over a convenient value
 132       \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
 133     end
 134     else begin
 135       localparam lower_clog2 = $clog2((DEPTH+1)/2);
 136       localparam lower_depth = 2 ** lower_clog2;
 137       wire T0, T1, T2, T3;
 138       if (&_TECHMAP_CONSTMSK_L_) begin
 139         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(lower_depth-1), .E(E), .Q(T0));
 140         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-lower_depth-1), .E(E), .Q(Q), .SO(T3));
 141       end
 142       else begin
 143         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
 144         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
 145         assign Q = L[lower_clog2] ? T2 : T0;
 146       end
 147       if (DEPTH == 2 * lower_depth)
 148           assign SO = T3;
 149     end
 150   endgenerate
 151 endmodule
 152
 153 module \$shiftx (A, B, Y);
 154   parameter A_SIGNED = 0;
 155   parameter B_SIGNED = 0;
 156   parameter A_WIDTH = 1;
 157   parameter B_WIDTH = 1;
 158   parameter Y_WIDTH = 1;
 159
 160   input [A_WIDTH-1:0] A;
 161   input [B_WIDTH-1:0] B;
 162   output [Y_WIDTH-1:0] Y;
 163
 164   parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
 165   parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
 166   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
 167   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 168
 169   function integer compute_num_leading_X_in_A;
 170     integer i, c;
 171   begin
 172     compute_num_leading_X_in_A = 0;
 173     c = 1;
 174     for (i = A_WIDTH-1; i >= 0; i=i-1) begin
 175       if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
 176         c = 0;
 177       compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
 178     end
 179   end
 180   endfunction
 181   localparam num_leading_X_in_A = compute_num_leading_X_in_A();
 182
 183   generate
 184     genvar i, j;
 185     // TODO: Check if this opt still necessary
 186     if (B_SIGNED) begin
 187       if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
 188         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
 189         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
 190       else
 191         wire _TECHMAP_FAIL_ = 1;
 192     end
 193     // Bit-blast
 194     else if (Y_WIDTH > 1) begin
 195       for (i = 0; i < Y_WIDTH; i++)
 196         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
 197     end
 198     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
 199     //   we can optimise by removing every other entry from A
 200     //   and popping the constant zero from B
 201     else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
 202       wire [(A_WIDTH+1)/2-1:0] A_i;
 203       for (i = 0; i < (A_WIDTH+1)/2; i++)
 204         assign A_i[i] = A[i*2];
 205       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
 206     end
 207     // Trim off any leading 1'bx -es in A, and resize B accordingly
 208     else if (num_leading_X_in_A > 0) begin
 209       localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
 210       localparam B_WIDTH_new = $clog2(A_WIDTH_new);
 211       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
 212     end
 213     else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
 214       wire _TECHMAP_FAIL_ = 1;
 215     end
 216     else if (B_WIDTH == 3) begin
 217       localparam a_width0 = 2 ** 2;
 218       localparam a_widthN = A_WIDTH - a_width0;
 219       wire T0, T1;
 220       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
 221       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
 222       MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
 223     end
 224     else if (B_WIDTH == 4) begin
 225       localparam a_width0 = 2 ** 2;
 226       localparam num_mux8 = A_WIDTH / a_width0;
 227       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
 228       wire [4-1:0] T;
 229       wire T0, T1;
 230       for (i = 0; i < 4; i++)
 231         if (i < num_mux8)
 232           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
 233         else if (i == num_mux8 && a_widthN > 0)
 234           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
 235         else
 236           assign T[i] = 1'bx;
 237       MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
 238       MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
 239       MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
 240     end
 241     else begin
 242       localparam a_width0 = 2 ** 4;
 243       localparam num_mux16 = A_WIDTH / a_width0;
 244       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
 245       wire [(2**(B_WIDTH-4))-1:0] T;
 246       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
 247         if (i < num_mux16)
 248           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
 249         else if (i == num_mux16 && a_widthN > 0) begin
 250           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
 251         end
 252         else
 253           assign T[i] = 1'bx;
 254       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
 255     end
 256   endgenerate
 257 endmodule