techlibs/xilinx/cells_map.v

   1
   2 module  \$_DFF_N_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
   3 module  \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
   4
   5 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
   6 module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
   7
   8 module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
   9 module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
  10 module  \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
  11 module  \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
  12
  13 module  \$_DFF_NN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
  14 module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
  15 module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
  16 module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
  17
  18 module \$lut (A, Y);
  19   parameter WIDTH = 0;
  20   parameter LUT = 0;
  21
  22   input [WIDTH-1:0] A;
  23   output Y;
  24
  25   generate
  26     if (WIDTH == 1) begin
  27       LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  28         .I0(A[0]));
  29     end else
  30     if (WIDTH == 2) begin
  31       LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  32         .I0(A[0]), .I1(A[1]));
  33     end else
  34     if (WIDTH == 3) begin
  35       LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  36         .I0(A[0]), .I1(A[1]), .I2(A[2]));
  37     end else
  38     if (WIDTH == 4) begin
  39       LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  40         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  41         .I3(A[3]));
  42     end else
  43     if (WIDTH == 5) begin
  44       LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  45         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  46         .I3(A[3]), .I4(A[4]));
  47     end else
  48     if (WIDTH == 6) begin
  49       LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  50         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  51         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  52     end else
  53     if (WIDTH == 7) begin
  54       wire T0, T1;
  55       LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
  56         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  57         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  58       LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
  59         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  60         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  61       MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
  62     end else
  63     if (WIDTH == 8) begin
  64       wire T0, T1, T2, T3, T4, T5;
  65       LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
  66         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  67         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  68       LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
  69         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  70         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  71       LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
  72         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  73         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  74       LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
  75         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  76         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  77       MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
  78       MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
  79       MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
  80     end else begin
  81       wire _TECHMAP_FAIL_ = 1;
  82     end
  83   endgenerate
  84 endmodule