techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // Convert negative-polarity reset to positive-polarity
  22 (* techmap_celltype = "$_DFF_NN0_" *)
  23 module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  24 (* techmap_celltype = "$_DFF_PN0_" *)
  25 module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  26 (* techmap_celltype = "$_DFF_NN1_" *)
  27 module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  28 (* techmap_celltype = "$_DFF_PN1_" *)
  29 module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  30
  31 module \$__SHREG_ (input C, input D, input E, output Q);
  32   parameter DEPTH = 0;
  33   parameter [DEPTH-1:0] INIT = 0;
  34   parameter CLKPOL = 1;
  35   parameter ENPOL = 2;
  36
  37   \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
  38 endmodule
  39
  40 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
  41   parameter DEPTH = 0;
  42   parameter [DEPTH-1:0] INIT = 0;
  43   parameter CLKPOL = 1;
  44   parameter ENPOL = 2;
  45
  46   // shregmap's INIT parameter shifts out LSB first;
  47   // however Xilinx expects MSB first
  48   function [DEPTH-1:0] brev;
  49     input [DEPTH-1:0] din;
  50     integer i;
  51     begin
  52       for (i = 0; i < DEPTH; i=i+1)
  53         brev[i] = din[DEPTH-1-i];
  54     end
  55   endfunction
  56   localparam [DEPTH-1:0] INIT_R = brev(INIT);
  57
  58   parameter _TECHMAP_CONSTMSK_L_ = 0;
  59
  60   wire CE;
  61   generate
  62     if (ENPOL == 0)
  63       assign CE = ~E;
  64     else if (ENPOL == 1)
  65       assign CE = E;
  66     else
  67       assign CE = 1'b1;
  68     if (DEPTH == 1) begin
  69       if (CLKPOL)
  70           FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  71       else
  72           FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  73     end else
  74     if (DEPTH <= 16) begin
  75       SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  76     end else
  77     if (DEPTH > 17 && DEPTH <= 32) begin
  78       SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  79     end else
  80     if (DEPTH > 33 && DEPTH <= 64) begin
  81       wire T0, T1, T2;
  82       SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
  83       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
  84       if (&_TECHMAP_CONSTMSK_L_)
  85         assign Q = T2;
  86       else
  87         MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
  88     end else
  89     if (DEPTH > 65 && DEPTH <= 96) begin
  90       wire T0, T1, T2, T3, T4, T5, T6;
  91       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  92       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  93       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
  94       if (&_TECHMAP_CONSTMSK_L_)
  95         assign Q = T4;
  96       else
  97         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
  98     end else
  99     if (DEPTH > 97 && DEPTH < 128) begin
 100       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
 101       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 102       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 103       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 104       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
 105       if (&_TECHMAP_CONSTMSK_L_)
 106         assign Q = T6;
 107       else
 108         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
 109     end
 110     else if (DEPTH == 128) begin
 111       wire T0, T1, T2, T3, T4, T5, T6;
 112       SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 113       SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 114       SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 115       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
 116       if (&_TECHMAP_CONSTMSK_L_)
 117         assign Q = T6;
 118       else
 119         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
 120     end
 121     // For fixed length, if just 1 over a convenient value, decompose
 122     else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin
 123       wire T;
 124       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));
 125       \$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));
 126     end
 127     // For variable length, if just 1 over a convenient value, then bump up one more
 128     else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)
 129       \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
 130     else begin
 131       localparam depth0 = 128;
 132       localparam num_srl128 = DEPTH / depth0;
 133       localparam depthN = DEPTH % depth0;
 134       wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;
 135       wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;
 136       assign S[0] = D;
 137       genvar i;
 138       for (i = 0; i < num_srl128; i++)
 139         \$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(S[i]),          .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));
 140
 141       if (depthN > 0)
 142         \$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));
 143
 144       if (&_TECHMAP_CONSTMSK_L_)
 145         assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];
 146       else
 147         assign Q = T[L[DEPTH-1:$clog2(depth0)]];
 148     end
 149   endgenerate
 150 endmodule
 151
 152 `ifdef MIN_MUX_INPUTS
 153 module \$__XILINX_SHIFTX (A, B, Y);
 154   parameter A_SIGNED = 0;
 155   parameter B_SIGNED = 0;
 156   parameter A_WIDTH = 1;
 157   parameter B_WIDTH = 1;
 158   parameter Y_WIDTH = 1;
 159
 160   input [A_WIDTH-1:0] A;
 161   input [B_WIDTH-1:0] B;
 162   output [Y_WIDTH-1:0] Y;
 163
 164   parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
 165   parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
 166   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
 167   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 168
 169   function integer A_WIDTH_trimmed;
 170     input integer start;
 171   begin
 172     A_WIDTH_trimmed = start;
 173     while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
 174       A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
 175   end
 176   endfunction
 177
 178   generate
 179     genvar i, j;
 180     // Bit-blast
 181     if (Y_WIDTH > 1) begin
 182       for (i = 0; i < Y_WIDTH; i++)
 183         \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
 184     end
 185     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
 186     //   we can optimise by removing every other entry from A
 187     //   and popping the constant zero from B
 188     else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
 189       wire [(A_WIDTH+1)/2-1:0] A_i;
 190       for (i = 0; i < (A_WIDTH+1)/2; i++)
 191         assign A_i[i] = A[i*2];
 192       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
 193     end
 194     // Trim off any leading 1'bx -es in A
 195     else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
 196       localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
 197       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
 198     end
 199     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
 200       wire _TECHMAP_FAIL_ = 1;
 201     end
 202     else if (A_WIDTH == 2) begin
 203       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
 204     end
 205     else if (A_WIDTH <= 4) begin
 206       wire [4-1:0] Ax;
 207       if (A_WIDTH == 4)
 208         assign Ax = A;
 209       else
 210         // Rather than extend with 1'bx which gets flattened to 1'b0
 211         // causing the "don't care" status to get lost, extend with
 212         // the same driver of F7B.I0 so that we can optimise F7B away
 213         // later
 214         assign Ax = {A[1], A};
 215       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
 216     end
 217     // Note that the following decompositions are 'backwards' in that
 218     // the LSBs are placed on the hard resources, and the soft resources
 219     // are used for MSBs.
 220     // This has the effect of more effectively utilising the hard mux;
 221     // take for example a 5:1 multiplexer, currently this would map as:
 222     //
 223     //     A[0] \___  __                             A[0] \__  __
 224     //     A[4] /   \|  \       whereas the more     A[1] /  \|  \
 225     //     A[1] _____|   |      obvious mapping      A[2] \___|   |
 226     //     A[2] _____|   |--    of MSBs to hard      A[3] /   |   |__
 227     //     A[3]______|   |      resources would      A[4] ____|   |
 228     //               |__/       lead to:             1'bx ____|   |
 229     //                ||                                      |__/
 230     //                ||                                       ||
 231     //              B[1:0]                                   B[1:2]
 232     //
 233     // Expectation would be that the 'forward' mapping (right) is more
 234     // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers
 235     // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)
 236     // but that the 'backwards' mapping (left) is more delay efficient
 237     // since smaller LUTs are faster than wider ones.
 238     else if (A_WIDTH <= 8) begin
 239       wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};
 240       wire T0 = B[2] ? Ax[4] : Ax[0];
 241       wire T1 = B[2] ? Ax[5] : Ax[1];
 242       wire T2 = B[2] ? Ax[6] : Ax[2];
 243       wire T3 = B[2] ? Ax[7] : Ax[3];
 244       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
 245     end
 246     else if (A_WIDTH <= 16) begin
 247       wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};
 248       wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
 249                      : B[3] ? Ax[ 8] : Ax[0];
 250       wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
 251                      : B[3] ? Ax[ 9] : Ax[1];
 252       wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]
 253                      : B[3] ? Ax[10] : Ax[2];
 254       wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]
 255                      : B[3] ? Ax[11] : Ax[3];
 256       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
 257     end
 258     else begin
 259       localparam num_mux16 = (A_WIDTH+15) / 16;
 260       localparam clog2_num_mux16 = $clog2(num_mux16);
 261       wire [num_mux16-1:0] T;
 262       wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};
 263       for (i = 0; i < num_mux16; i++)
 264         \$__XILINX_SHIFTX  #(
 265           .A_SIGNED(A_SIGNED),
 266           .B_SIGNED(B_SIGNED),
 267           .A_WIDTH(16),
 268           .B_WIDTH(4),
 269           .Y_WIDTH(Y_WIDTH)
 270         ) fpga_mux (
 271           .A(Ax[i*16+:16]),
 272           .B(B[3:0]),
 273           .Y(T[i])
 274         );
 275       \$__XILINX_SHIFTX  #(
 276           .A_SIGNED(A_SIGNED),
 277           .B_SIGNED(B_SIGNED),
 278           .A_WIDTH(num_mux16),
 279           .B_WIDTH(clog2_num_mux16),
 280           .Y_WIDTH(Y_WIDTH)
 281       ) _TECHMAP_REPLACE_ (
 282           .A(T),
 283           .B(B[B_WIDTH-1-:clog2_num_mux16]),
 284           .Y(Y));
 285     end
 286   endgenerate
 287 endmodule
 288
 289 (* techmap_celltype = "$__XILINX_SHIFTX" *)
 290 module _90__XILINX_SHIFTX (A, B, Y);
 291   parameter A_SIGNED = 0;
 292   parameter B_SIGNED = 0;
 293   parameter A_WIDTH = 1;
 294   parameter B_WIDTH = 1;
 295   parameter Y_WIDTH = 1;
 296
 297   input [A_WIDTH-1:0] A;
 298   input [B_WIDTH-1:0] B;
 299   output [Y_WIDTH-1:0] Y;
 300
 301   \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
 302 endmodule
 303
 304 module \$_MUX_ (A, B, S, Y);
 305   input A, B, S;
 306   output Y;
 307   generate
 308     if (`MIN_MUX_INPUTS == 2)
 309       \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));
 310     else
 311       wire _TECHMAP_FAIL_ = 1;
 312   endgenerate
 313 endmodule
 314
 315 module \$_MUX4_ (A, B, C, D, S, T, Y);
 316   input A, B, C, D, S, T;
 317   output Y;
 318   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));
 319 endmodule
 320
 321 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 322   input A, B, C, D, E, F, G, H, S, T, U;
 323   output Y;
 324   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 325 endmodule
 326
 327 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 328   input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 329   output Y;
 330   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 331 endmodule
 332 `endif
 333
 334 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
 335   output O;
 336   input I0, I1, I2, I3, S0, S1;
 337   wire T0, T1;
 338   parameter _TECHMAP_BITS_CONNMAP_ = 0;
 339   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
 340   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
 341   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
 342   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
 343   parameter _TECHMAP_CONSTMSK_S0_ = 0;
 344   parameter _TECHMAP_CONSTVAL_S0_ = 0;
 345   parameter _TECHMAP_CONSTMSK_S1_ = 0;
 346   parameter _TECHMAP_CONSTVAL_S1_ = 0;
 347   if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
 348     assign T0 = I1;
 349   else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
 350     assign T0 = I0;
 351   else
 352     MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
 353   if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
 354     assign T1 = I3;
 355   else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
 356     assign T1 = I2;
 357   else
 358     MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
 359   if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
 360     assign O = T1;
 361   else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
 362     assign O = T0;
 363   else
 364     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 365 endmodule