techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 module \$__SHREG_ (input C, input D, input E, output Q);
  22   parameter DEPTH = 0;
  23   parameter [DEPTH-1:0] INIT = 0;
  24   parameter CLKPOL = 1;
  25   parameter ENPOL = 2;
  26
  27   \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
  28 endmodule
  29
  30 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
  31   parameter DEPTH = 0;
  32   parameter [DEPTH-1:0] INIT = 0;
  33   parameter CLKPOL = 1;
  34   parameter ENPOL = 2;
  35
  36   // shregmap's INIT parameter shifts out LSB first;
  37   // however Xilinx expects MSB first
  38   function [DEPTH-1:0] brev;
  39     input [DEPTH-1:0] din;
  40     integer i;
  41     begin
  42       for (i = 0; i < DEPTH; i=i+1)
  43         brev[i] = din[DEPTH-1-i];
  44     end
  45   endfunction
  46   localparam [DEPTH-1:0] INIT_R = brev(INIT);
  47
  48   parameter _TECHMAP_CONSTMSK_L_ = 0;
  49
  50   wire CE;
  51   generate
  52     if (ENPOL == 0)
  53       assign CE = ~E;
  54     else if (ENPOL == 1)
  55       assign CE = E;
  56     else
  57       assign CE = 1'b1;
  58     if (DEPTH == 1) begin
  59       if (CLKPOL)
  60           FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  61       else
  62           FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  63     end else
  64     if (DEPTH <= 16) begin
  65       SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  66     end else
  67     if (DEPTH > 17 && DEPTH <= 32) begin
  68       SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  69     end else
  70     if (DEPTH > 33 && DEPTH <= 64) begin
  71       wire T0, T1, T2;
  72       SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
  73       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
  74       if (&_TECHMAP_CONSTMSK_L_)
  75         assign Q = T2;
  76       else
  77         MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
  78     end else
  79     if (DEPTH > 65 && DEPTH <= 96) begin
  80       wire T0, T1, T2, T3, T4, T5, T6;
  81       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  82       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  83       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
  84       if (&_TECHMAP_CONSTMSK_L_)
  85         assign Q = T4;
  86       else
  87         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
  88     end else
  89     if (DEPTH > 97 && DEPTH < 128) begin
  90       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
  91       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  92       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  93       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
  94       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
  95       if (&_TECHMAP_CONSTMSK_L_)
  96         assign Q = T6;
  97       else
  98         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
  99     end
 100     else if (DEPTH == 128) begin
 101       wire T0, T1, T2, T3, T4, T5, T6;
 102       SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 103       SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 104       SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 105       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
 106       if (&_TECHMAP_CONSTMSK_L_)
 107         assign Q = T6;
 108       else
 109         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
 110     end
 111     // For fixed length, if just 1 over a convenient value, decompose
 112     else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin
 113       wire T;
 114       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));
 115       \$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));
 116     end
 117     // For variable length, if just 1 over a convenient value, then bump up one more
 118     else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)
 119       \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
 120     else begin
 121       localparam depth0 = 128;
 122       localparam num_srl128 = DEPTH / depth0;
 123       localparam depthN = DEPTH % depth0;
 124       wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;
 125       wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;
 126       assign S[0] = D;
 127       genvar i;
 128       for (i = 0; i < num_srl128; i++)
 129         \$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(S[i]),          .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));
 130
 131       if (depthN > 0)
 132         \$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));
 133
 134       if (&_TECHMAP_CONSTMSK_L_)
 135         assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];
 136       else
 137         assign Q = T[L[DEPTH-1:$clog2(depth0)]];
 138     end
 139   endgenerate
 140 endmodule
 141
 142 `ifdef MIN_MUX_INPUTS
 143 module \$__XILINX_SHIFTX (A, B, Y);
 144   parameter A_SIGNED = 0;
 145   parameter B_SIGNED = 0;
 146   parameter A_WIDTH = 1;
 147   parameter B_WIDTH = 1;
 148   parameter Y_WIDTH = 1;
 149
 150   (* force_downto *)
 151   input [A_WIDTH-1:0] A;
 152   (* force_downto *)
 153   input [B_WIDTH-1:0] B;
 154   (* force_downto *)
 155   output [Y_WIDTH-1:0] Y;
 156
 157   parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
 158   parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
 159   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
 160   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 161
 162   function integer A_WIDTH_trimmed;
 163     input integer start;
 164   begin
 165     A_WIDTH_trimmed = start;
 166     while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
 167       A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
 168   end
 169   endfunction
 170
 171   generate
 172     genvar i, j;
 173     // Bit-blast
 174     if (Y_WIDTH > 1) begin
 175       for (i = 0; i < Y_WIDTH; i++)
 176         \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
 177     end
 178     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
 179     //   we can optimise by removing every other entry from A
 180     //   and popping the constant zero from B
 181     else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
 182       wire [(A_WIDTH+1)/2-1:0] A_i;
 183       for (i = 0; i < (A_WIDTH+1)/2; i++)
 184         assign A_i[i] = A[i*2];
 185       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
 186     end
 187     // Trim off any leading 1'bx -es in A
 188     else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
 189       localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
 190       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
 191     end
 192     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
 193       wire _TECHMAP_FAIL_ = 1;
 194     end
 195     else if (A_WIDTH == 2) begin
 196       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
 197     end
 198     else if (A_WIDTH <= 4) begin
 199       wire [4-1:0] Ax;
 200       if (A_WIDTH == 4)
 201         assign Ax = A;
 202       else
 203         // Rather than extend with 1'bx which gets flattened to 1'b0
 204         // causing the "don't care" status to get lost, extend with
 205         // the same driver of F7B.I0 so that we can optimise F7B away
 206         // later
 207         assign Ax = {A[1], A};
 208       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
 209     end
 210     // Note that the following decompositions are 'backwards' in that
 211     // the LSBs are placed on the hard resources, and the soft resources
 212     // are used for MSBs.
 213     // This has the effect of more effectively utilising the hard mux;
 214     // take for example a 5:1 multiplexer, currently this would map as:
 215     //
 216     //     A[0] \___  __                             A[0] \__  __
 217     //     A[4] /   \|  \       whereas the more     A[1] /  \|  \
 218     //     A[1] _____|   |      obvious mapping      A[2] \___|   |
 219     //     A[2] _____|   |--    of MSBs to hard      A[3] /   |   |__
 220     //     A[3]______|   |      resources would      A[4] ____|   |
 221     //               |__/       lead to:             1'bx ____|   |
 222     //                ||                                      |__/
 223     //                ||                                       ||
 224     //              B[1:0]                                   B[1:2]
 225     //
 226     // Expectation would be that the 'forward' mapping (right) is more
 227     // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers
 228     // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)
 229     // but that the 'backwards' mapping (left) is more delay efficient
 230     // since smaller LUTs are faster than wider ones.
 231     else if (A_WIDTH <= 8) begin
 232       wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};
 233       wire T0 = B[2] ? Ax[4] : Ax[0];
 234       wire T1 = B[2] ? Ax[5] : Ax[1];
 235       wire T2 = B[2] ? Ax[6] : Ax[2];
 236       wire T3 = B[2] ? Ax[7] : Ax[3];
 237       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
 238     end
 239     else if (A_WIDTH <= 16) begin
 240       wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};
 241       wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
 242                      : B[3] ? Ax[ 8] : Ax[0];
 243       wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
 244                      : B[3] ? Ax[ 9] : Ax[1];
 245       wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]
 246                      : B[3] ? Ax[10] : Ax[2];
 247       wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]
 248                      : B[3] ? Ax[11] : Ax[3];
 249       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
 250     end
 251     else begin
 252       localparam num_mux16 = (A_WIDTH+15) / 16;
 253       localparam clog2_num_mux16 = $clog2(num_mux16);
 254       wire [num_mux16-1:0] T;
 255       wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};
 256       for (i = 0; i < num_mux16; i++)
 257         \$__XILINX_SHIFTX  #(
 258           .A_SIGNED(A_SIGNED),
 259           .B_SIGNED(B_SIGNED),
 260           .A_WIDTH(16),
 261           .B_WIDTH(4),
 262           .Y_WIDTH(Y_WIDTH)
 263         ) fpga_mux (
 264           .A(Ax[i*16+:16]),
 265           .B(B[3:0]),
 266           .Y(T[i])
 267         );
 268       \$__XILINX_SHIFTX  #(
 269           .A_SIGNED(A_SIGNED),
 270           .B_SIGNED(B_SIGNED),
 271           .A_WIDTH(num_mux16),
 272           .B_WIDTH(clog2_num_mux16),
 273           .Y_WIDTH(Y_WIDTH)
 274       ) _TECHMAP_REPLACE_ (
 275           .A(T),
 276           .B(B[B_WIDTH-1-:clog2_num_mux16]),
 277           .Y(Y));
 278     end
 279   endgenerate
 280 endmodule
 281
 282 (* techmap_celltype = "$__XILINX_SHIFTX" *)
 283 module _90__XILINX_SHIFTX (A, B, Y);
 284   parameter A_SIGNED = 0;
 285   parameter B_SIGNED = 0;
 286   parameter A_WIDTH = 1;
 287   parameter B_WIDTH = 1;
 288   parameter Y_WIDTH = 1;
 289
 290   (* force_downto *)
 291   input [A_WIDTH-1:0] A;
 292   (* force_downto *)
 293   input [B_WIDTH-1:0] B;
 294   (* force_downto *)
 295   output [Y_WIDTH-1:0] Y;
 296
 297   \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
 298 endmodule
 299
 300 module \$_MUX_ (A, B, S, Y);
 301   input A, B, S;
 302   output Y;
 303   generate
 304     if (`MIN_MUX_INPUTS == 2)
 305       \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));
 306     else
 307       wire _TECHMAP_FAIL_ = 1;
 308   endgenerate
 309 endmodule
 310
 311 module \$_MUX4_ (A, B, C, D, S, T, Y);
 312   input A, B, C, D, S, T;
 313   output Y;
 314   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));
 315 endmodule
 316
 317 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 318   input A, B, C, D, E, F, G, H, S, T, U;
 319   output Y;
 320   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 321 endmodule
 322
 323 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 324   input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 325   output Y;
 326   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 327 endmodule
 328 `endif
 329
 330 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
 331   output O;
 332   input I0, I1, I2, I3, S0, S1;
 333   wire T0, T1;
 334   parameter _TECHMAP_BITS_CONNMAP_ = 0;
 335   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
 336   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
 337   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
 338   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
 339   parameter _TECHMAP_CONSTMSK_S0_ = 0;
 340   parameter _TECHMAP_CONSTVAL_S0_ = 0;
 341   parameter _TECHMAP_CONSTMSK_S1_ = 0;
 342   parameter _TECHMAP_CONSTVAL_S1_ = 0;
 343   if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
 344     assign T0 = I1;
 345   else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
 346     assign T0 = I0;
 347   else
 348     MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
 349   if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
 350     assign T1 = I3;
 351   else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
 352     assign T1 = I2;
 353   else
 354     MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
 355   if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
 356     assign O = T1;
 357   else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
 358     assign O = T0;
 359   else
 360     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 361 endmodule
 362
 363 module \$__XILINX_TINOUTPAD (input I, OE, output O, inout IO);
 364   IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE), .IO(IO));
 365 endmodule
 366
 367 module \$__XILINX_TOUTPAD (input I, OE, output O);
 368   OBUFT _TECHMAP_REPLACE_ (.I(I), .O(O), .T(~OE));
 369 endmodule