techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // Convert negative-polarity reset to positive-polarity
  22 (* techmap_celltype = "$_DFF_NN0_" *)
  23 module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  24 (* techmap_celltype = "$_DFF_PN0_" *)
  25 module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  26 (* techmap_celltype = "$_DFF_NN1_" *)
  27 module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  28 (* techmap_celltype = "$_DFF_PN1_" *)
  29 module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  30
  31 module \$__SHREG_ (input C, input D, input E, output Q);
  32   parameter DEPTH = 0;
  33   parameter [DEPTH-1:0] INIT = 0;
  34   parameter CLKPOL = 1;
  35   parameter ENPOL = 2;
  36
  37   \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
  38 endmodule
  39
  40 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
  41   parameter DEPTH = 0;
  42   parameter [DEPTH-1:0] INIT = 0;
  43   parameter CLKPOL = 1;
  44   parameter ENPOL = 2;
  45
  46   // shregmap's INIT parameter shifts out LSB first;
  47   // however Xilinx expects MSB first
  48   function [DEPTH-1:0] brev;
  49     input [DEPTH-1:0] din;
  50     integer i;
  51     begin
  52       for (i = 0; i < DEPTH; i=i+1)
  53         brev[i] = din[DEPTH-1-i];
  54     end
  55   endfunction
  56   localparam [DEPTH-1:0] INIT_R = brev(INIT);
  57
  58   parameter _TECHMAP_CONSTMSK_L_ = 0;
  59   parameter _TECHMAP_CONSTVAL_L_ = 0;
  60
  61   wire CE;
  62   generate
  63     if (ENPOL == 0)
  64       assign CE = ~E;
  65     else if (ENPOL == 1)
  66       assign CE = E;
  67     else
  68       assign CE = 1'b1;
  69     if (DEPTH == 1) begin
  70       if (CLKPOL)
  71           FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  72       else
  73           FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  74     end else
  75     if (DEPTH <= 16) begin
  76       SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  77     end else
  78     if (DEPTH > 17 && DEPTH <= 32) begin
  79       SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  80     end else
  81     if (DEPTH > 33 && DEPTH <= 64) begin
  82       wire T0, T1, T2;
  83       SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
  84       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
  85       if (&_TECHMAP_CONSTMSK_L_)
  86         assign Q = T2;
  87       else
  88         MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
  89     end else
  90     if (DEPTH > 65 && DEPTH <= 96) begin
  91       wire T0, T1, T2, T3, T4, T5, T6;
  92       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  93       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  94       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
  95       if (&_TECHMAP_CONSTMSK_L_)
  96         assign Q = T4;
  97       else
  98         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
  99     end else
 100     if (DEPTH > 97 && DEPTH < 128) begin
 101       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
 102       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 103       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 104       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 105       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
 106       if (&_TECHMAP_CONSTMSK_L_)
 107         assign Q = T6;
 108       else
 109         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
 110     end
 111     else if (DEPTH == 128) begin
 112       wire T0, T1, T2, T3, T4, T5, T6;
 113       SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 114       SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 115       SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 116       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
 117       if (&_TECHMAP_CONSTMSK_L_)
 118         assign Q = T6;
 119       else
 120         \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
 121     end
 122     else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
 123       // Handle cases where fixed-length depth is
 124       // just 1 over a convenient value
 125       \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
 126     end
 127     else begin
 128       localparam lower_clog2 = $clog2((DEPTH+1)/2);
 129       localparam lower_depth = 2 ** lower_clog2;
 130       wire T0, T1, T2, T3;
 131       if (&_TECHMAP_CONSTMSK_L_) begin
 132         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(lower_depth-1), .E(E), .Q(T0));
 133         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-lower_depth-1), .E(E), .Q(Q), .SO(T3));
 134       end
 135       else begin
 136         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
 137         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
 138         assign Q = L[lower_clog2] ? T2 : T0;
 139       end
 140       if (DEPTH == 2 * lower_depth)
 141           assign SO = T3;
 142     end
 143   endgenerate
 144 endmodule
 145
 146 `ifdef MIN_MUX_INPUTS
 147 module \$__XILINX_SHIFTX (A, B, Y);
 148   parameter A_SIGNED = 0;
 149   parameter B_SIGNED = 0;
 150   parameter A_WIDTH = 1;
 151   parameter B_WIDTH = 1;
 152   parameter Y_WIDTH = 1;
 153
 154   input [A_WIDTH-1:0] A;
 155   input [B_WIDTH-1:0] B;
 156   output [Y_WIDTH-1:0] Y;
 157
 158   parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
 159   parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
 160   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
 161   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 162
 163   function integer A_WIDTH_trimmed;
 164     input integer start;
 165   begin
 166     A_WIDTH_trimmed = start;
 167     while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
 168       A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
 169   end
 170   endfunction
 171
 172   generate
 173     genvar i, j;
 174     // Bit-blast
 175     if (Y_WIDTH > 1) begin
 176       for (i = 0; i < Y_WIDTH; i++)
 177         \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
 178     end
 179     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
 180     //   we can optimise by removing every other entry from A
 181     //   and popping the constant zero from B
 182     else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
 183       wire [(A_WIDTH+1)/2-1:0] A_i;
 184       for (i = 0; i < (A_WIDTH+1)/2; i++)
 185         assign A_i[i] = A[i*2];
 186       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
 187     end
 188     // Trim off any leading 1'bx -es in A
 189     else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
 190       localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
 191       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
 192     end
 193     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
 194       wire _TECHMAP_FAIL_ = 1;
 195     end
 196     else if (A_WIDTH == 2) begin
 197       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
 198     end
 199     else if (A_WIDTH <= 2 ** 2) begin
 200       wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A};
 201       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y));
 202     end
 203     else if (A_WIDTH <= 2 ** 3) begin
 204       // Rather than extend with 1'bx which gets flattened to 1'b0
 205       // causing the "don't care" state to get lost, extend with MSB
 206       // so that we can recognise again later when mapping MUXF78
 207       wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A};
 208       wire T0 = B[0] ? Ax[1] : Ax[0];
 209       wire T1 = B[0] ? Ax[3] : Ax[2];
 210       wire T2 = B[0] ? Ax[5] : Ax[4];
 211       wire T3 = B[0] ? Ax[7] : Ax[6];
 212       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[1]), .S1(B[2]), .O(Y));
 213     end
 214     else if (A_WIDTH <= 2 ** 4) begin
 215       // Rather than extend with 1'bx which gets flattened to 1'b0
 216       // causing the "don't care" state to get lost, extend with MSB
 217       // so that we can recognise again later when mapping MUXF78
 218       wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A};
 219       wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2]
 220                      : B[0] ? Ax[ 1] : Ax[ 0];
 221       wire T1 = B[1] ? B[0] ? Ax[ 7] : Ax[ 6]
 222                      : B[0] ? Ax[ 5] : Ax[ 4];
 223       wire T2 = B[1] ? B[0] ? Ax[11] : Ax[10]
 224                      : B[0] ? Ax[ 9] : Ax[ 8];
 225       wire T3 = B[1] ? B[0] ? Ax[15] : Ax[14]
 226                      : B[0] ? Ax[13] : Ax[12];
 227       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[2]), .S1(B[3]), .O(Y));
 228     end
 229     else begin
 230       localparam num_mux16 = (A_WIDTH+15) / 16;
 231       localparam clog2_num_mux16 = $clog2(num_mux16);
 232       wire [num_mux16-1:0] T;
 233       wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};
 234       for (i = 0; i < num_mux16; i++)
 235         \$__XILINX_SHIFTX  #(
 236           .A_SIGNED(A_SIGNED),
 237           .B_SIGNED(B_SIGNED),
 238           .A_WIDTH(16),
 239           .B_WIDTH(4),
 240           .Y_WIDTH(Y_WIDTH)
 241         ) fpga_mux (
 242           .A(Ax[i*16+:16]),
 243           .B(B[3:0]),
 244           .Y(T[i])
 245         );
 246       \$__XILINX_SHIFTX  #(
 247           .A_SIGNED(A_SIGNED),
 248           .B_SIGNED(B_SIGNED),
 249           .A_WIDTH(num_mux16),
 250           .B_WIDTH(clog2_num_mux16),
 251           .Y_WIDTH(Y_WIDTH)
 252       ) _TECHMAP_REPLACE_ (
 253           .A(T),
 254           .B(B[B_WIDTH-1-:clog2_num_mux16]),
 255           .Y(Y));
 256     end
 257   endgenerate
 258 endmodule
 259
 260 (* techmap_celltype = "$__XILINX_SHIFTX" *)
 261 module _90__XILINX_SHIFTX (A, B, Y);
 262   parameter A_SIGNED = 0;
 263   parameter B_SIGNED = 0;
 264   parameter A_WIDTH = 1;
 265   parameter B_WIDTH = 1;
 266   parameter Y_WIDTH = 1;
 267
 268   input [A_WIDTH-1:0] A;
 269   input [B_WIDTH-1:0] B;
 270   output [Y_WIDTH-1:0] Y;
 271
 272   \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
 273 endmodule
 274
 275 module \$_MUX_ (A, B, S, Y);
 276   input A, B, S;
 277   output Y;
 278   generate
 279     if (`MIN_MUX_INPUTS == 2)
 280       \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));
 281     else
 282       wire _TECHMAP_FAIL_ = 1;
 283   endgenerate
 284 endmodule
 285
 286 module \$_MUX4_ (A, B, C, D, S, T, Y);
 287   input A, B, C, D, S, T;
 288   output Y;
 289   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));
 290 endmodule
 291
 292 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 293   input A, B, C, D, E, F, G, H, S, T, U;
 294   output Y;
 295   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 296 endmodule
 297
 298 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 299   input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 300   output Y;
 301   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 302 endmodule
 303 `endif
 304
 305 `ifndef _ABC
 306 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
 307   output O;
 308   input I0, I1, I2, I3, S0, S1;
 309   wire T0, T1;
 310   parameter _TECHMAP_BITS_CONNMAP_ = 0;
 311   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
 312   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
 313   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
 314   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
 315   parameter _TECHMAP_CONSTMSK_S0_ = 0;
 316   parameter _TECHMAP_CONSTVAL_S0_ = 0;
 317   parameter _TECHMAP_CONSTMSK_S1_ = 0;
 318   parameter _TECHMAP_CONSTVAL_S1_ = 0;
 319   if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
 320     assign T0 = I1;
 321   else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
 322     assign T0 = I0;
 323   else
 324     MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
 325   if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
 326     assign T1 = I3;
 327   else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
 328     assign T1 = I2;
 329   else
 330     MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
 331   if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
 332     assign O = T1;
 333   else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
 334     assign O = T0;
 335   else
 336     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 337 endmodule
 338 `endif