techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // Convert negative-polarity reset to positive-polarity
  22 (* techmap_celltype = "$_DFF_NN0_" *)
  23 module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  24 (* techmap_celltype = "$_DFF_PN0_" *)
  25 module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  26 (* techmap_celltype = "$_DFF_NN1_" *)
  27 module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  28 (* techmap_celltype = "$_DFF_PN1_" *)
  29 module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  30
  31 module \$__SHREG_ (input C, input D, input E, output Q);
  32   parameter DEPTH = 0;
  33   parameter [DEPTH-1:0] INIT = 0;
  34   parameter CLKPOL = 1;
  35   parameter ENPOL = 2;
  36
  37   \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
  38 endmodule
  39
  40 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
  41   parameter DEPTH = 0;
  42   parameter [DEPTH-1:0] INIT = 0;
  43   parameter CLKPOL = 1;
  44   parameter ENPOL = 2;
  45
  46   // shregmap's INIT parameter shifts out LSB first;
  47   // however Xilinx expects MSB first
  48   function [DEPTH-1:0] brev;
  49     input [DEPTH-1:0] din;
  50     integer i;
  51     begin
  52       for (i = 0; i < DEPTH; i=i+1)
  53         brev[i] = din[DEPTH-1-i];
  54     end
  55   endfunction
  56   localparam [DEPTH-1:0] INIT_R = brev(INIT);
  57
  58   parameter _TECHMAP_CONSTMSK_L_ = 0;
  59
  60   wire CE;
  61   generate
  62     if (ENPOL == 0)
  63       assign CE = ~E;
  64     else if (ENPOL == 1)
  65       assign CE = E;
  66     else
  67       assign CE = 1'b1;
  68     if (DEPTH == 1) begin
  69       if (CLKPOL)
  70           FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  71       else
  72           FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  73     end else
  74     if (DEPTH <= 16) begin
  75       SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  76     end else
  77     if (DEPTH > 17 && DEPTH <= 32) begin
  78       SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  79     end else
  80     if (DEPTH > 33 && DEPTH <= 64) begin
  81       wire T0, T1, T2;
  82       SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
  83       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
  84       if (&_TECHMAP_CONSTMSK_L_)
  85         assign Q = T2;
  86       else
  87         MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
  88     end else
  89     if (DEPTH > 65 && DEPTH <= 96) begin
  90       wire T0, T1, T2, T3, T4, T5, T6;
  91       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  92       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  93       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
  94       if (&_TECHMAP_CONSTMSK_L_)
  95         assign Q = T4;
  96       else begin
  97         MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
  98         MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
  99         MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
 100       end
 101     end else
 102     if (DEPTH > 97 && DEPTH < 128) begin
 103       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
 104       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 105       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 106       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 107       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
 108       if (&_TECHMAP_CONSTMSK_L_)
 109         assign Q = T6;
 110       else begin
 111         MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
 112         MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
 113         MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
 114       end
 115     end
 116     else if (DEPTH == 128) begin
 117       wire T0, T1, T2, T3, T4, T5, T6;
 118       SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 119       SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 120       SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 121       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
 122       if (&_TECHMAP_CONSTMSK_L_)
 123         assign Q = T6;
 124       else begin
 125         wire T7, T8;
 126         MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
 127         MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
 128         MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
 129       end
 130     end
 131     // For fixed length, if just 1 over a convenient value, decompose
 132     else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin
 133       wire T;
 134       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));
 135       \$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));
 136     end
 137     // For variable length, if just 1 over a convenient value, then bump up one more
 138     else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)
 139       \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
 140     else begin
 141       localparam depth0 = 128;
 142       localparam num_srl128 = DEPTH / depth0;
 143       localparam depthN = DEPTH % depth0;
 144       wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;
 145       wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;
 146       assign S[0] = D;
 147       genvar i;
 148       for (i = 0; i < num_srl128; i++)
 149         \$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(S[i]),          .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));
 150
 151       if (depthN > 0)
 152         \$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));
 153
 154       if (&_TECHMAP_CONSTMSK_L_)
 155         assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];
 156       else
 157         assign Q = T[L[DEPTH-1:$clog2(depth0)]];
 158     end
 159   endgenerate
 160 endmodule