techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // Convert negative-polarity reset to positive-polarity
  22 (* techmap_celltype = "$_DFF_NN0_" *)
  23 module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  24 (* techmap_celltype = "$_DFF_PN0_" *)
  25 module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  26 (* techmap_celltype = "$_DFF_NN1_" *)
  27 module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  28 (* techmap_celltype = "$_DFF_PN1_" *)
  29 module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
  30
  31 module \$__SHREG_ (input C, input D, input E, output Q);
  32   parameter DEPTH = 0;
  33   parameter [DEPTH-1:0] INIT = 0;
  34   parameter CLKPOL = 1;
  35   parameter ENPOL = 2;
  36
  37   \$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
  38 endmodule
  39
  40 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
  41   parameter DEPTH = 0;
  42   parameter [DEPTH-1:0] INIT = 0;
  43   parameter CLKPOL = 1;
  44   parameter ENPOL = 2;
  45
  46   // shregmap's INIT parameter shifts out LSB first;
  47   // however Xilinx expects MSB first
  48   function [DEPTH-1:0] brev;
  49     input [DEPTH-1:0] din;
  50     integer i;
  51     begin
  52       for (i = 0; i < DEPTH; i=i+1)
  53         brev[i] = din[DEPTH-1-i];
  54     end
  55   endfunction
  56   localparam [DEPTH-1:0] INIT_R = brev(INIT);
  57
  58   parameter _TECHMAP_CONSTMSK_L_ = 0;
  59   parameter _TECHMAP_CONSTVAL_L_ = 0;
  60
  61   wire CE;
  62   generate
  63     if (ENPOL == 0)
  64       assign CE = ~E;
  65     else if (ENPOL == 1)
  66       assign CE = E;
  67     else
  68       assign CE = 1'b1;
  69     if (DEPTH == 1) begin
  70       if (CLKPOL)
  71           FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  72       else
  73           FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
  74     end else
  75     if (DEPTH <= 16) begin
  76       SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  77     end else
  78     if (DEPTH > 17 && DEPTH <= 32) begin
  79       SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
  80     end else
  81     if (DEPTH > 33 && DEPTH <= 64) begin
  82       wire T0, T1, T2;
  83       SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
  84       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
  85       if (&_TECHMAP_CONSTMSK_L_)
  86         assign Q = T2;
  87       else
  88         MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
  89     end else
  90     if (DEPTH > 65 && DEPTH <= 96) begin
  91       wire T0, T1, T2, T3, T4, T5, T6;
  92       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
  93       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
  94       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
  95       if (&_TECHMAP_CONSTMSK_L_)
  96         assign Q = T4;
  97       else
  98         wire TA, TB;
  99         \$__XILINX_MUXF7x2 fpga_hard_mux7 (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S(L[5]), .O0(TA), .O1(TB));
 100         MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
 101     end else
 102     if (DEPTH > 97 && DEPTH < 128) begin
 103       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
 104       SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 105       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 106       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 107       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
 108       if (&_TECHMAP_CONSTMSK_L_)
 109         assign Q = T6;
 110       else
 111         wire TA, TB;
 112         \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S(L[5]), .O0(TA), .O1(TB));
 113         MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
 114     end
 115     else if (DEPTH == 128) begin
 116       wire T0, T1, T2, T3, T4, T5, T6;
 117       SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
 118       SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
 119       SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
 120       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
 121       if (&_TECHMAP_CONSTMSK_L_)
 122         assign Q = T6;
 123       else begin
 124         wire TA, TB;
 125         \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S(L[5]), .O0(T7), .O1(T8));
 126         MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
 127       end
 128     end
 129     else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
 130       // Handle cases where fixed-length depth is
 131       // just 1 over a convenient value
 132       \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
 133     end
 134     else begin
 135       localparam lower_clog2 = $clog2((DEPTH+1)/2);
 136       localparam lower_depth = 2 ** lower_clog2;
 137       wire T0, T1, T2, T3;
 138       if (&_TECHMAP_CONSTMSK_L_) begin
 139         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(lower_depth-1), .E(E), .Q(T0));
 140         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-lower_depth-1), .E(E), .Q(Q), .SO(T3));
 141       end
 142       else begin
 143         \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
 144         \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
 145         assign Q = L[lower_clog2] ? T2 : T0;
 146       end
 147       if (DEPTH == 2 * lower_depth)
 148           assign SO = T3;
 149     end
 150   endgenerate
 151 endmodule
 152
 153 `ifdef MIN_MUX_INPUTS
 154 module \$__XILINX_SHIFTX (A, B, Y);
 155   parameter A_SIGNED = 0;
 156   parameter B_SIGNED = 0;
 157   parameter A_WIDTH = 1;
 158   parameter B_WIDTH = 1;
 159   parameter Y_WIDTH = 1;
 160
 161   input [A_WIDTH-1:0] A;
 162   input [B_WIDTH-1:0] B;
 163   output [Y_WIDTH-1:0] Y;
 164
 165   parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
 166   parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
 167   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
 168   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 169
 170   function integer A_WIDTH_trimmed;
 171     input integer start;
 172   begin
 173     A_WIDTH_trimmed = start;
 174     while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
 175       A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
 176   end
 177   endfunction
 178
 179   generate
 180     genvar i, j;
 181     // Bit-blast
 182     if (Y_WIDTH > 1) begin
 183       for (i = 0; i < Y_WIDTH; i++)
 184         \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
 185     end
 186     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
 187     //   we can optimise by removing every other entry from A
 188     //   and popping the constant zero from B
 189     else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
 190       wire [(A_WIDTH+1)/2-1:0] A_i;
 191       for (i = 0; i < (A_WIDTH+1)/2; i++)
 192         assign A_i[i] = A[i*2];
 193       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
 194     end
 195     // Trim off any leading 1'bx -es in A
 196     else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
 197       localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
 198       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
 199     end
 200     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
 201       wire _TECHMAP_FAIL_ = 1;
 202     end
 203     else if (A_WIDTH <= 2 ** 3) begin
 204       localparam a_width0 = 2 ** 2;
 205       localparam a_widthN = A_WIDTH - a_width0;
 206       wire T0, T1;
 207       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
 208       if (a_widthN > 1)
 209         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
 210       else
 211         assign T1 = A[A_WIDTH-1];
 212       MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[2]), .O(Y));
 213     end
 214     else if (A_WIDTH <= 2 ** 4) begin
 215       localparam a_width0 = 2 ** 2;
 216       localparam num_mux8 = A_WIDTH / a_width0;
 217       localparam a_widthN = A_WIDTH % a_width0;
 218       wire [a_width0-1:0] T;
 219       for (i = 0; i < a_width0; i++)
 220         if (i < num_mux8)
 221           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
 222         else if (i == num_mux8 && a_widthN > 1)
 223           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
 224         else
 225           assign T[i] = A[A_WIDTH-1];
 226       wire TA, TB;
 227       \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T[0]), .I1(T[2]), .I2(T[4]), .I3(T[6]), .S(B[2]), .O0(TA), .O1(TB));
 228       MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(B[3]), .O(Q));
 229     end
 230     else begin
 231       localparam a_width0 = 2 ** 4;
 232       localparam num_mux16 = A_WIDTH / a_width0;
 233       localparam a_widthN = A_WIDTH % a_width0;
 234       wire [num_mux16 + (a_widthN > 0 ? 1 : 0) - 1:0] T;
 235       for (i = 0; i < num_mux16; i++)
 236         \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
 237       if (a_widthN > 0) begin
 238         if (a_widthN > 1)
 239           \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
 240         else
 241           assign T[num_mux16] = A[A_WIDTH-1];
 242       end
 243       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(num_mux16 + (a_widthN > 0 ? 1 : 0)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
 244     end
 245   endgenerate
 246 endmodule
 247
 248 (* techmap_celltype = "$__XILINX_SHIFTX" *)
 249 module _90__XILINX_SHIFTX (A, B, Y);
 250   parameter A_SIGNED = 0;
 251   parameter B_SIGNED = 0;
 252   parameter A_WIDTH = 1;
 253   parameter B_WIDTH = 1;
 254   parameter Y_WIDTH = 1;
 255
 256   input [A_WIDTH-1:0] A;
 257   input [B_WIDTH-1:0] B;
 258   output [Y_WIDTH-1:0] Y;
 259
 260   \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
 261 endmodule
 262
 263 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 264 input A, B, C, D, E, F, G, H, S, T, U;
 265 output Y;
 266   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 267 endmodule
 268
 269 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 270 input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 271 output Y;
 272   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 273 endmodule
 274 `endif
 275
 276 `ifndef _ABC
 277 module \$__XILINX_MUXF7x2 (O0, O1, I0, I1, I2, I3, S);
 278   output O0, O1;
 279   input I0, I1, I2, I3, S;
 280   parameter _TECHMAP_BITS_CONNMAP_ = 0;
 281   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
 282   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
 283   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
 284   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
 285   parameter _TECHMAP_CONSTMSK_S_ = 0;
 286   parameter _TECHMAP_CONSTVAL_S_ = 0;
 287   if (_TECHMAP_CONSTMSK_S_ && _TECHMAP_CONSTVAL_S_ === 1'b1)
 288     assign O0 = I1;
 289   else if (_TECHMAP_CONSTMSK_S_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
 290     assign O0 = I0;
 291   else
 292     MUXF7 mux7a (.I0(I0), .I1(I1), .S(S), .O(O0));
 293   if (_TECHMAP_CONSTMSK_S_ && _TECHMAP_CONSTVAL_S_ === 1'b1)
 294     assign O1 = I3;
 295   else if (_TECHMAP_CONSTMSK_S_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
 296     assign O1 = I2;
 297   else
 298     MUXF7 mux7b (.I0(I2), .I1(I3), .S(S), .O(O1));
 299 endmodule
 300 `endif