techlibs/xilinx/cells_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 module \$shiftx (A, B, Y);
  21   parameter A_SIGNED = 0;
  22   parameter B_SIGNED = 0;
  23   parameter A_WIDTH = 1;
  24   parameter B_WIDTH = 1;
  25   parameter Y_WIDTH = 1;
  26
  27   input [A_WIDTH-1:0] A;
  28   input [B_WIDTH-1:0] B;
  29   output [Y_WIDTH-1:0] Y;
  30
  31   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
  32   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
  33
  34   generate
  35     genvar i, j;
  36     if (B_SIGNED) begin
  37       if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
  38         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
  39         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
  40       else
  41         wire _TECHMAP_FAIL_ = 1;
  42     end
  43     else if (Y_WIDTH > 1) begin
  44       wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_bitty = B/Y_WIDTH;
  45       for (i = 0; i < Y_WIDTH; i++) begin
  46         wire [A_WIDTH/Y_WIDTH-1:0] A_i;
  47         for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
  48           assign A_i[j] = A[j*Y_WIDTH+i];
  49         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_bitty), .Y(Y[i]));
  50       end
  51     end
  52     else if (B_WIDTH < 3) begin
  53       wire _TECHMAP_FAIL_ = 1;
  54     end
  55     else if (B_WIDTH == 3) begin
  56       localparam a_width0 = 2 ** 2;
  57       localparam a_widthN = A_WIDTH - a_width0;
  58       wire T0, T1;
  59       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
  60       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
  61       MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
  62     end
  63     else if (B_WIDTH == 4) begin
  64       localparam a_width0 = 2 ** 2;
  65       localparam num_mux8 = A_WIDTH / a_width0;
  66       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
  67       wire [4-1:0] T;
  68       wire T0, T1;
  69       for (i = 0; i < 4; i++)
  70         if (i < num_mux8)
  71           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
  72         else if (i == num_mux8 && a_widthN > 0)
  73           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
  74         else
  75           assign T[i] = 1'bx;
  76       MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
  77       MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
  78       MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
  79     end
  80     else begin
  81       localparam a_width0 = 2 ** 4;
  82       localparam num_mux16 = A_WIDTH / a_width0;
  83       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
  84       wire [(2**(B_WIDTH-4))-1:0] T;
  85       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
  86         if (i < num_mux16)
  87           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
  88         else if (i == num_mux16 && a_widthN > 0) begin
  89           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
  90         end
  91         else
  92           assign T[i] = 1'bx;
  93       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
  94     end
  95   endgenerate
  96 endmodule