techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(output O, input I);
  33   parameter IOSTANDARD = "default";
  34   parameter IBUF_LOW_PWR = 0;
  35   assign O = I;
  36 endmodule
  37
  38 module OBUF(output O, input I);
  39   parameter IOSTANDARD = "default";
  40   parameter DRIVE = 12;
  41   parameter SLEW = "SLOW";
  42   assign O = I;
  43 endmodule
  44
  45 module BUFG(output O, input I);
  46   assign O = I;
  47 endmodule
  48
  49 module BUFGCTRL(
  50     output O,
  51     input I0, input I1,
  52     input S0, input S1,
  53     input CE0, input CE1,
  54     input IGNORE0, input IGNORE1);
  55
  56 parameter [0:0] INIT_OUT = 1'b0;
  57 parameter PRESELECT_I0 = "FALSE";
  58 parameter PRESELECT_I1 = "FALSE";
  59 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  60 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  61 parameter [0:0] IS_S0_INVERTED = 1'b0;
  62 parameter [0:0] IS_S1_INVERTED = 1'b0;
  63 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  64 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  65
  66 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  67 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  68 wire S0_true = (S0 ^ IS_S0_INVERTED);
  69 wire S1_true = (S1 ^ IS_S1_INVERTED);
  70
  71 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  72
  73 endmodule
  74
  75 module BUFHCE(output O, input I, input CE);
  76
  77 parameter [0:0] INIT_OUT = 1'b0;
  78 parameter CE_TYPE = "SYNC";
  79 parameter [0:0] IS_CE_INVERTED = 1'b0;
  80
  81 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  82
  83 endmodule
  84
  85 // module OBUFT(output O, input I, T);
  86 //   assign O = T ? 1'bz : I;
  87 // endmodule
  88
  89 // module IOBUF(inout IO, output O, input I, T);
  90 //   assign O = IO, IO = T ? 1'bz : I;
  91 // endmodule
  92
  93 module INV(output O, input I);
  94   assign O = !I;
  95 endmodule
  96
  97 module LUT1(output O, input I0);
  98   parameter [1:0] INIT = 0;
  99   assign O = I0 ? INIT[1] : INIT[0];
 100 endmodule
 101
 102 module LUT2(output O, input I0, I1);
 103   parameter [3:0] INIT = 0;
 104   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 105   assign O = I0 ? s1[1] : s1[0];
 106 endmodule
 107
 108 module LUT3(output O, input I0, I1, I2);
 109   parameter [7:0] INIT = 0;
 110   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 111   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 112   assign O = I0 ? s1[1] : s1[0];
 113 endmodule
 114
 115 module LUT4(output O, input I0, I1, I2, I3);
 116   parameter [15:0] INIT = 0;
 117   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 118   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 119   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT5(output O, input I0, I1, I2, I3, I4);
 124   parameter [31:0] INIT = 0;
 125   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 126   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 127   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 128   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 129   assign O = I0 ? s1[1] : s1[0];
 130 endmodule
 131
 132 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 133   parameter [63:0] INIT = 0;
 134   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 135   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 136   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 137   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 138   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 139   assign O = I0 ? s1[1] : s1[0];
 140 endmodule
 141
 142 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 143   parameter [63:0] INIT = 0;
 144   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 145   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 146   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 147   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 148   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 149   assign O6 = I0 ? s1[1] : s1[0];
 150
 151   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 152   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 153   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 154   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 155   assign O5 = I0 ? s5_1[1] : s5_1[0];
 156 endmodule
 157
 158 module MUXCY(output O, input CI, DI, S);
 159   assign O = S ? CI : DI;
 160 endmodule
 161
 162 (* abc_box_id = 1, lib_whitebox *)
 163 module MUXF7(output O, input I0, I1, S);
 164   assign O = S ? I1 : I0;
 165 endmodule
 166
 167 (* abc_box_id = 2, lib_whitebox *)
 168 module MUXF8(output O, input I0, I1, S);
 169   assign O = S ? I1 : I0;
 170 endmodule
 171
 172 `ifdef _ABC
 173 (* abc_box_id = 3, lib_whitebox *)
 174 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
 175   assign O = S1 ? (S0 ? I3 : I2)
 176                 : (S0 ? I1 : I0);
 177 endmodule
 178 `endif
 179
 180 module XORCY(output O, input CI, LI);
 181   assign O = CI ^ LI;
 182 endmodule
 183
 184 (* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
 185 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
 186   assign O = S ^ {CO[2:0], CI | CYINIT};
 187   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 188   assign CO[1] = S[1] ? CO[0] : DI[1];
 189   assign CO[2] = S[2] ? CO[1] : DI[2];
 190   assign CO[3] = S[3] ? CO[2] : DI[3];
 191 endmodule
 192
 193 `ifdef _EXPLICIT_CARRY
 194
 195 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 196   parameter CYINIT_FABRIC = 0;
 197   wire CI_COMBINE;
 198   if(CYINIT_FABRIC) begin
 199     assign CI_COMBINE = CI_INIT;
 200   end else begin
 201     assign CI_COMBINE = CI;
 202   end
 203   assign CO_CHAIN = S ? CI_COMBINE : DI;
 204   assign CO_FABRIC = S ? CI_COMBINE : DI;
 205   assign O = S ^ CI_COMBINE;
 206 endmodule
 207
 208 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 209   assign CO_CHAIN = S ? CI : DI;
 210   assign CO_FABRIC = S ? CI : DI;
 211   assign O = S ^ CI;
 212 endmodule
 213
 214 `endif
 215
 216 module FDRE (output reg Q, input C, CE, D, R);
 217   parameter [0:0] INIT = 1'b0;
 218   parameter [0:0] IS_C_INVERTED = 1'b0;
 219   parameter [0:0] IS_D_INVERTED = 1'b0;
 220   parameter [0:0] IS_R_INVERTED = 1'b0;
 221   initial Q <= INIT;
 222   generate case (|IS_C_INVERTED)
 223     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 224     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 225   endcase endgenerate
 226 endmodule
 227
 228 module FDSE (output reg Q, input C, CE, D, S);
 229   parameter [0:0] INIT = 1'b1;
 230   parameter [0:0] IS_C_INVERTED = 1'b0;
 231   parameter [0:0] IS_D_INVERTED = 1'b0;
 232   parameter [0:0] IS_S_INVERTED = 1'b0;
 233   initial Q <= INIT;
 234   generate case (|IS_C_INVERTED)
 235     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 236     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 237   endcase endgenerate
 238 endmodule
 239
 240 module FDCE (output reg Q, input C, CE, D, CLR);
 241   parameter [0:0] INIT = 1'b0;
 242   parameter [0:0] IS_C_INVERTED = 1'b0;
 243   parameter [0:0] IS_D_INVERTED = 1'b0;
 244   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 245   initial Q <= INIT;
 246   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 247     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 248     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 249     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 250     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 251   endcase endgenerate
 252 endmodule
 253
 254 module FDPE (output reg Q, input C, CE, D, PRE);
 255   parameter [0:0] INIT = 1'b1;
 256   parameter [0:0] IS_C_INVERTED = 1'b0;
 257   parameter [0:0] IS_D_INVERTED = 1'b0;
 258   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 259   initial Q <= INIT;
 260   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 261     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 262     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 263     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 264     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 265   endcase endgenerate
 266 endmodule
 267
 268 module FDRE_1 (output reg Q, input C, CE, D, R);
 269   parameter [0:0] INIT = 1'b0;
 270   initial Q <= INIT;
 271   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 272 endmodule
 273
 274 module FDSE_1 (output reg Q, input C, CE, D, S);
 275   parameter [0:0] INIT = 1'b1;
 276   initial Q <= INIT;
 277   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 278 endmodule
 279
 280 module FDCE_1 (output reg Q, input C, CE, D, CLR);
 281   parameter [0:0] INIT = 1'b0;
 282   initial Q <= INIT;
 283   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 284 endmodule
 285
 286 module FDPE_1 (output reg Q, input C, CE, D, PRE);
 287   parameter [0:0] INIT = 1'b1;
 288   initial Q <= INIT;
 289   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 290 endmodule
 291
 292 (* abc_box_id = 5, abc_scc_break="D,WE" *)
 293 module RAM32X1D (
 294   output DPO, SPO,
 295   input  D, WCLK, WE,
 296   input  A0, A1, A2, A3, A4,
 297   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 298 );
 299   parameter INIT = 32'h0;
 300   parameter IS_WCLK_INVERTED = 1'b0;
 301   wire [4:0] a = {A4, A3, A2, A1, A0};
 302   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 303   reg [31:0] mem = INIT;
 304   assign SPO = mem[a];
 305   assign DPO = mem[dpra];
 306   wire clk = WCLK ^ IS_WCLK_INVERTED;
 307   always @(posedge clk) if (WE) mem[a] <= D;
 308 endmodule
 309
 310 (* abc_box_id = 6, abc_scc_break="D,WE" *)
 311 module RAM64X1D (
 312   output DPO, SPO,
 313   input  D, WCLK, WE,
 314   input  A0, A1, A2, A3, A4, A5,
 315   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 316 );
 317   parameter INIT = 64'h0;
 318   parameter IS_WCLK_INVERTED = 1'b0;
 319   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 320   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 321   reg [63:0] mem = INIT;
 322   assign SPO = mem[a];
 323   assign DPO = mem[dpra];
 324   wire clk = WCLK ^ IS_WCLK_INVERTED;
 325   always @(posedge clk) if (WE) mem[a] <= D;
 326 endmodule
 327
 328 (* abc_box_id = 7, abc_scc_break="D,WE" *)
 329 module RAM128X1D (
 330   output       DPO, SPO,
 331   input        D, WCLK, WE,
 332   input  [6:0] A, DPRA
 333 );
 334   parameter INIT = 128'h0;
 335   parameter IS_WCLK_INVERTED = 1'b0;
 336   reg [127:0] mem = INIT;
 337   assign SPO = mem[A];
 338   assign DPO = mem[DPRA];
 339   wire clk = WCLK ^ IS_WCLK_INVERTED;
 340   always @(posedge clk) if (WE) mem[A] <= D;
 341 endmodule
 342
 343 module SRL16E (
 344   output Q,
 345   input A0, A1, A2, A3, CE, CLK, D
 346 );
 347   parameter [15:0] INIT = 16'h0000;
 348   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 349
 350   reg [15:0] r = INIT;
 351   assign Q = r[{A3,A2,A1,A0}];
 352   generate
 353     if (IS_CLK_INVERTED) begin
 354       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 355     end
 356     else
 357         always @(posedge CLK) if (CE) r <= { r[14:0], D };
 358   endgenerate
 359 endmodule
 360
 361 module SRLC32E (
 362   output Q,
 363   output Q31,
 364   input [4:0] A,
 365   input CE, CLK, D
 366 );
 367   parameter [31:0] INIT = 32'h00000000;
 368   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 369
 370   reg [31:0] r = INIT;
 371   assign Q31 = r[31];
 372   assign Q = r[A];
 373   generate
 374     if (IS_CLK_INVERTED) begin
 375       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 376     end
 377     else
 378       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 379   endgenerate
 380 endmodule
 381
 382 module DSP48E1 (
 383     output [29:0] ACOUT,
 384     output [17:0] BCOUT,
 385     output CARRYCASCOUT,
 386     output [3:0] CARRYOUT,
 387     output MULTSIGNOUT,
 388     output OVERFLOW,
 389     output reg [47:0] P,
 390     output PATTERNBDETECT,
 391     output PATTERNDETECT,
 392     output [47:0] PCOUT,
 393     output UNDERFLOW,
 394     input [29:0] A,
 395     input [29:0] ACIN,
 396     input [3:0] ALUMODE,
 397     input [17:0] B,
 398     input [17:0] BCIN,
 399     input [47:0] C,
 400     input CARRYCASCIN,
 401     input CARRYIN,
 402     input [2:0] CARRYINSEL,
 403     input CEA1,
 404     input CEA2,
 405     input CEAD,
 406     input CEALUMODE,
 407     input CEB1,
 408     input CEB2,
 409     input CEC,
 410     input CECARRYIN,
 411     input CECTRL,
 412     input CED,
 413     input CEINMODE,
 414     input CEM,
 415     input CEP,
 416     input CLK,
 417     input [24:0] D,
 418     input [4:0] INMODE,
 419     input MULTSIGNIN,
 420     input [6:0] OPMODE,
 421     input [47:0] PCIN,
 422     input RSTA,
 423     input RSTALLCARRYIN,
 424     input RSTALUMODE,
 425     input RSTB,
 426     input RSTC,
 427     input RSTCTRL,
 428     input RSTD,
 429     input RSTINMODE,
 430     input RSTM,
 431     input RSTP
 432 );
 433     parameter integer ACASCREG = 1;
 434     parameter integer ADREG = 1;
 435     parameter integer ALUMODEREG = 1;
 436     parameter integer AREG = 1;
 437     parameter AUTORESET_PATDET = "NO_RESET";
 438     parameter A_INPUT = "DIRECT";
 439     parameter integer BCASCREG = 1;
 440     parameter integer BREG = 1;
 441     parameter B_INPUT = "DIRECT";
 442     parameter integer CARRYINREG = 1;
 443     parameter integer CARRYINSELREG = 1;
 444     parameter integer CREG = 1;
 445     parameter integer DREG = 1;
 446     parameter integer INMODEREG = 1;
 447     parameter integer MREG = 1;
 448     parameter integer OPMODEREG = 1;
 449     parameter integer PREG = 1;
 450     parameter SEL_MASK = "MASK";
 451     parameter SEL_PATTERN = "PATTERN";
 452     parameter USE_DPORT = "FALSE";
 453     parameter USE_MULT = "MULTIPLY";
 454     parameter USE_PATTERN_DETECT = "NO_PATDET";
 455     parameter USE_SIMD = "ONE48";
 456     parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
 457     parameter [47:0] PATTERN = 48'h000000000000;
 458     parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
 459     parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
 460     parameter [0:0] IS_CLK_INVERTED = 1'b0;
 461     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
 462     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 463
 464     initial begin
 465 `ifdef __ICARUS__
 466         if (ACASCREG != 0)          $fatal(1, "Unsupported ACASCREG value");
 467         if (ADREG != 0)             $fatal(1, "Unsupported ADREG value");
 468         if (ALUMODEREG != 0)        $fatal(1, "Unsupported ALUMODEREG value");
 469         if (AREG == 2)              $fatal(1, "Unsupported AREG value");
 470         if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
 471         if (A_INPUT != "DIRECT")    $fatal(1, "Unsupported A_INPUT value");
 472         if (BCASCREG != 0)          $fatal(1, "Unsupported BCASCREG value");
 473         if (BREG == 2)              $fatal(1, "Unsupported BREG value");
 474         if (B_INPUT != "DIRECT")    $fatal(1, "Unsupported B_INPUT value");
 475         if (CARRYINREG != 0)        $fatal(1, "Unsupported CARRYINREG value");
 476         if (CARRYINSELREG != 0)     $fatal(1, "Unsupported CARRYINSELREG value");
 477         if (CREG != 0)              $fatal(1, "Unsupported CREG value");
 478         if (DREG != 0)              $fatal(1, "Unsupported DREG value");
 479         if (INMODEREG != 0)         $fatal(1, "Unsupported INMODEREG value");
 480         if (MREG != 0)              $fatal(1, "Unsupported MREG value");
 481         if (OPMODEREG != 0)         $fatal(1, "Unsupported OPMODEREG value");
 482         //if (PREG != 0)              $fatal(1, "Unsupported PREG value");
 483         if (SEL_MASK != "MASK")     $fatal(1, "Unsupported SEL_MASK value");
 484         if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
 485         if (USE_DPORT != "FALSE")   $fatal(1, "Unsupported USE_DPORT value");
 486         if (USE_MULT != "MULTIPLY") $fatal(1, "Unsupported USE_MULT value");
 487         if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value");
 488         if (USE_SIMD != "ONE48")    $fatal(1, "Unsupported USE_SIMD value");
 489         if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
 490         if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value");
 491         if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value");
 492         if (IS_INMODE_INVERTED != 5'b0) $fatal(1, "Unsupported IS_INMODE_INVERTED value");
 493         if (IS_OPMODE_INVERTED != 7'b0) $fatal(1, "Unsupported IS_OPMODE_INVERTED value");
 494 `endif
 495     end
 496
 497     reg [29:0] Ar;
 498     reg [17:0] Br;
 499     reg [47:0] Pr;
 500     generate
 501         if (AREG == 1) begin always @(posedge CLK) if (CEA2) Ar <= A; end
 502         else           always @* Ar <= A;
 503         if (BREG == 1) begin always @(posedge CLK) if (CEB2) Br <= B; end
 504         else           always @* Br <= B;
 505     endgenerate
 506
 507     always @* begin
 508         Pr <= {48{1'bx}};
 509 `ifdef __ICARUS__
 510         if (INMODE != 4'b0000)      $fatal(1, "Unsupported INMODE value");
 511         if (ALUMODE != 4'b0000)     $fatal(1, "Unsupported ALUMODE value");
 512         if (OPMODE != 7'b000101)    $fatal(1, "Unsupported OPMODE value");
 513         if (CARRYINSEL != 3'b000)   $fatal(1, "Unsupported CARRYINSEL value");
 514         if (ACIN != 30'b0)          $fatal(1, "Unsupported ACIN value");
 515         if (BCIN != 18'b0)          $fatal(1, "Unsupported BCIN value");
 516         if (PCIN != 48'b0)          $fatal(1, "Unsupported PCIN value");
 517         if (CARRYIN != 1'b0)        $fatal(1, "Unsupported CARRYIN value");
 518 `endif
 519         Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
 520     end
 521
 522     generate
 523         if (PREG == 1) begin always @(posedge CLK) if (CEP) P <= Pr; end
 524         else           always @* P <= Pr;
 525     endgenerate
 526
 527 endmodule