2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // See Xilinx UG953 and UG474 for a description of the cell types below.
21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
32 module IBUF(output O, input I);
33 parameter IOSTANDARD = "default";
34 parameter IBUF_LOW_PWR = 0;
38 module OBUF(output O, input I);
39 parameter IOSTANDARD = "default";
41 parameter SLEW = "SLOW";
45 module BUFG(output O, input I);
54 input IGNORE0, input IGNORE1);
56 parameter [0:0] INIT_OUT = 1'b0;
57 parameter PRESELECT_I0 = "FALSE";
58 parameter PRESELECT_I1 = "FALSE";
59 parameter [0:0] IS_CE0_INVERTED = 1'b0;
60 parameter [0:0] IS_CE1_INVERTED = 1'b0;
61 parameter [0:0] IS_S0_INVERTED = 1'b0;
62 parameter [0:0] IS_S1_INVERTED = 1'b0;
63 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
64 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
66 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
67 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
68 wire S0_true = (S0 ^ IS_S0_INVERTED);
69 wire S1_true = (S1 ^ IS_S1_INVERTED);
71 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
75 module BUFHCE(output O, input I, input CE);
77 parameter [0:0] INIT_OUT = 1'b0;
78 parameter CE_TYPE = "SYNC";
79 parameter [0:0] IS_CE_INVERTED = 1'b0;
81 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
85 // module OBUFT(output O, input I, T);
86 // assign O = T ? 1'bz : I;
89 // module IOBUF(inout IO, output O, input I, T);
90 // assign O = IO, IO = T ? 1'bz : I;
93 module INV(output O, input I);
97 module LUT1(output O, input I0);
98 parameter [1:0] INIT = 0;
99 assign O = I0 ? INIT[1] : INIT[0];
102 module LUT2(output O, input I0, I1);
103 parameter [3:0] INIT = 0;
104 wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
105 assign O = I0 ? s1[1] : s1[0];
108 module LUT3(output O, input I0, I1, I2);
109 parameter [7:0] INIT = 0;
110 wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
111 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
112 assign O = I0 ? s1[1] : s1[0];
115 module LUT4(output O, input I0, I1, I2, I3);
116 parameter [15:0] INIT = 0;
117 wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
118 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
119 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
120 assign O = I0 ? s1[1] : s1[0];
123 module LUT5(output O, input I0, I1, I2, I3, I4);
124 parameter [31:0] INIT = 0;
125 wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
126 wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
127 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
128 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
129 assign O = I0 ? s1[1] : s1[0];
132 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
133 parameter [63:0] INIT = 0;
134 wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
135 wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
136 wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
137 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
138 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
139 assign O = I0 ? s1[1] : s1[0];
142 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
143 parameter [63:0] INIT = 0;
144 wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
145 wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
146 wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
147 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
148 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
149 assign O6 = I0 ? s1[1] : s1[0];
151 wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
152 wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
153 wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
154 wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
155 assign O5 = I0 ? s5_1[1] : s5_1[0];
158 module MUXCY(output O, input CI, DI, S);
159 assign O = S ? CI : DI;
162 (* abc_box_id = 1, lib_whitebox *)
163 module MUXF7(output O, input I0, I1, S);
164 assign O = S ? I1 : I0;
167 (* abc_box_id = 2, lib_whitebox *)
168 module MUXF8(output O, input I0, I1, S);
169 assign O = S ? I1 : I0;
172 module XORCY(output O, input CI, LI);
176 (* abc_box_id = 3, abc_carry, lib_whitebox *)
177 module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
178 assign O = S ^ {CO[2:0], CI | CYINIT};
179 assign CO[0] = S[0] ? CI | CYINIT : DI[0];
180 assign CO[1] = S[1] ? CO[0] : DI[1];
181 assign CO[2] = S[2] ? CO[1] : DI[2];
182 assign CO[3] = S[3] ? CO[2] : DI[3];
185 `ifdef _EXPLICIT_CARRY
187 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
188 parameter CYINIT_FABRIC = 0;
190 if(CYINIT_FABRIC) begin
191 assign CI_COMBINE = CI_INIT;
193 assign CI_COMBINE = CI;
195 assign CO_CHAIN = S ? CI_COMBINE : DI;
196 assign CO_FABRIC = S ? CI_COMBINE : DI;
197 assign O = S ^ CI_COMBINE;
200 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
201 assign CO_CHAIN = S ? CI : DI;
202 assign CO_FABRIC = S ? CI : DI;
208 (* abc_box_id = 6, abc_flop /*, lib_whitebox */ *)
209 module FDRE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R);
210 parameter [0:0] INIT = 1'b0;
211 parameter [0:0] IS_C_INVERTED = 1'b0;
212 parameter [0:0] IS_D_INVERTED = 1'b0;
213 parameter [0:0] IS_R_INVERTED = 1'b0;
216 generate case (|IS_C_INVERTED)
217 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
218 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
221 always @* if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
225 (* abc_box_id = 7, abc_flop /*, lib_whitebox*/ *)
226 module FDSE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S);
227 parameter [0:0] INIT = 1'b0;
228 parameter [0:0] IS_C_INVERTED = 1'b0;
229 parameter [0:0] IS_D_INVERTED = 1'b0;
230 parameter [0:0] IS_S_INVERTED = 1'b0;
233 generate case (|IS_C_INVERTED)
234 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
235 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
238 always @* if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
242 (* abc_box_id = 8, abc_flop /*, lib_whitebox*/ *)
243 module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR);
244 parameter [0:0] INIT = 1'b0;
245 parameter [0:0] IS_C_INVERTED = 1'b0;
246 parameter [0:0] IS_D_INVERTED = 1'b0;
247 parameter [0:0] IS_CLR_INVERTED = 1'b0;
250 generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
251 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
252 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
253 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
254 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
257 generate case (|IS_CLR_INVERTED)
258 1'b0: always @* if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
259 1'b1: always @* if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
264 (* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *)
265 module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
266 parameter [0:0] INIT = 1'b0;
267 parameter [0:0] IS_C_INVERTED = 1'b0;
268 parameter [0:0] IS_D_INVERTED = 1'b0;
269 parameter [0:0] IS_PRE_INVERTED = 1'b0;
272 generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
273 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
274 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
275 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
276 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
279 generate case (|IS_PRE_INVERTED)
280 1'b0: always @* if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
281 1'b1: always @* if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
286 module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
287 parameter [0:0] INIT = 1'b0;
289 always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
292 module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
293 parameter [0:0] INIT = 1'b1;
295 always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
298 module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
299 parameter [0:0] INIT = 1'b0;
301 always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
304 module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
305 parameter [0:0] INIT = 1'b1;
307 always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
310 (* abc_box_id = 4 /*, lib_whitebox*/ *)
314 input A0, A1, A2, A3, A4, A5,
315 input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
317 parameter INIT = 64'h0;
318 parameter IS_WCLK_INVERTED = 1'b0;
319 wire [5:0] a = {A5, A4, A3, A2, A1, A0};
320 wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
321 reg [63:0] mem = INIT;
323 assign DPO = mem[dpra];
325 wire clk = WCLK ^ IS_WCLK_INVERTED;
326 always @(posedge clk) if (WE) mem[a] <= D;
330 (* abc_box_id = 5 /*, lib_whitebox*/ *)
336 parameter INIT = 128'h0;
337 parameter IS_WCLK_INVERTED = 1'b0;
338 reg [127:0] mem = INIT;
340 assign DPO = mem[DPRA];
342 wire clk = WCLK ^ IS_WCLK_INVERTED;
343 always @(posedge clk) if (WE) mem[A] <= D;
348 (* abc_flop_q *) output Q,
349 input A0, A1, A2, A3, CE, CLK, D
351 parameter [15:0] INIT = 16'h0000;
352 parameter [0:0] IS_CLK_INVERTED = 1'b0;
355 assign Q = r[{A3,A2,A1,A0}];
357 if (IS_CLK_INVERTED) begin
358 always @(negedge CLK) if (CE) r <= { r[14:0], D };
361 always @(posedge CLK) if (CE) r <= { r[14:0], D };
366 (* abc_flop_q *) output Q,
371 parameter [31:0] INIT = 32'h00000000;
372 parameter [0:0] IS_CLK_INVERTED = 1'b0;
378 if (IS_CLK_INVERTED) begin
379 always @(negedge CLK) if (CE) r <= { r[30:0], D };
382 always @(posedge CLK) if (CE) r <= { r[30:0], D };