techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(output O, input I);
  33   parameter IOSTANDARD = "default";
  34   parameter IBUF_LOW_PWR = 0;
  35   assign O = I;
  36 endmodule
  37
  38 module OBUF(output O, input I);
  39   parameter IOSTANDARD = "default";
  40   parameter DRIVE = 12;
  41   parameter SLEW = "SLOW";
  42   assign O = I;
  43 endmodule
  44
  45 module BUFG(output O, input I);
  46   assign O = I;
  47 endmodule
  48
  49 module BUFGCTRL(
  50     output O,
  51     input I0, input I1,
  52     input S0, input S1,
  53     input CE0, input CE1,
  54     input IGNORE0, input IGNORE1);
  55
  56 parameter [0:0] INIT_OUT = 1'b0;
  57 parameter PRESELECT_I0 = "FALSE";
  58 parameter PRESELECT_I1 = "FALSE";
  59 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  60 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  61 parameter [0:0] IS_S0_INVERTED = 1'b0;
  62 parameter [0:0] IS_S1_INVERTED = 1'b0;
  63 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  64 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  65
  66 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  67 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  68 wire S0_true = (S0 ^ IS_S0_INVERTED);
  69 wire S1_true = (S1 ^ IS_S1_INVERTED);
  70
  71 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  72
  73 endmodule
  74
  75 module BUFHCE(output O, input I, input CE);
  76
  77 parameter [0:0] INIT_OUT = 1'b0;
  78 parameter CE_TYPE = "SYNC";
  79 parameter [0:0] IS_CE_INVERTED = 1'b0;
  80
  81 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  82
  83 endmodule
  84
  85 // module OBUFT(output O, input I, T);
  86 //   assign O = T ? 1'bz : I;
  87 // endmodule
  88
  89 // module IOBUF(inout IO, output O, input I, T);
  90 //   assign O = IO, IO = T ? 1'bz : I;
  91 // endmodule
  92
  93 module INV(output O, input I);
  94   assign O = !I;
  95 endmodule
  96
  97 module LUT1(output O, input I0);
  98   parameter [1:0] INIT = 0;
  99   assign O = I0 ? INIT[1] : INIT[0];
 100 endmodule
 101
 102 module LUT2(output O, input I0, I1);
 103   parameter [3:0] INIT = 0;
 104   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 105   assign O = I0 ? s1[1] : s1[0];
 106 endmodule
 107
 108 module LUT3(output O, input I0, I1, I2);
 109   parameter [7:0] INIT = 0;
 110   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 111   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 112   assign O = I0 ? s1[1] : s1[0];
 113 endmodule
 114
 115 module LUT4(output O, input I0, I1, I2, I3);
 116   parameter [15:0] INIT = 0;
 117   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 118   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 119   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT5(output O, input I0, I1, I2, I3, I4);
 124   parameter [31:0] INIT = 0;
 125   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 126   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 127   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 128   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 129   assign O = I0 ? s1[1] : s1[0];
 130 endmodule
 131
 132 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 133   parameter [63:0] INIT = 0;
 134   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 135   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 136   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 137   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 138   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 139   assign O = I0 ? s1[1] : s1[0];
 140 endmodule
 141
 142 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 143   parameter [63:0] INIT = 0;
 144   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 145   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 146   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 147   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 148   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 149   assign O6 = I0 ? s1[1] : s1[0];
 150
 151   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 152   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 153   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 154   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 155   assign O5 = I0 ? s5_1[1] : s5_1[0];
 156 endmodule
 157
 158 module MUXCY(output O, input CI, DI, S);
 159   assign O = S ? CI : DI;
 160 endmodule
 161
 162 (* abc_box_id = 1, lib_whitebox *)
 163 module MUXF7(output O, input I0, I1, S);
 164   assign O = S ? I1 : I0;
 165 endmodule
 166
 167 (* abc_box_id = 2, lib_whitebox *)
 168 module MUXF8(output O, input I0, I1, S);
 169   assign O = S ? I1 : I0;
 170 endmodule
 171
 172 module XORCY(output O, input CI, LI);
 173   assign O = CI ^ LI;
 174 endmodule
 175
 176 (* abc_box_id = 4, lib_whitebox *)
 177 module CARRY4(
 178   (* abc_carry *)
 179   output [3:0] CO,
 180   output [3:0] O,
 181   (* abc_carry *)
 182   input        CI,
 183   input        CYINIT,
 184   input  [3:0] DI, S
 185 );
 186   assign O = S ^ {CO[2:0], CI | CYINIT};
 187   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 188   assign CO[1] = S[1] ? CO[0] : DI[1];
 189   assign CO[2] = S[2] ? CO[1] : DI[2];
 190   assign CO[3] = S[3] ? CO[2] : DI[3];
 191 endmodule
 192
 193 `ifdef _EXPLICIT_CARRY
 194
 195 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 196   parameter CYINIT_FABRIC = 0;
 197   wire CI_COMBINE;
 198   if(CYINIT_FABRIC) begin
 199     assign CI_COMBINE = CI_INIT;
 200   end else begin
 201     assign CI_COMBINE = CI;
 202   end
 203   assign CO_CHAIN = S ? CI_COMBINE : DI;
 204   assign CO_FABRIC = S ? CI_COMBINE : DI;
 205   assign O = S ^ CI_COMBINE;
 206 endmodule
 207
 208 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 209   assign CO_CHAIN = S ? CI : DI;
 210   assign CO_FABRIC = S ? CI : DI;
 211   assign O = S ^ CI;
 212 endmodule
 213
 214 `endif
 215
 216 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 217
 218 module FDRE ((* abc_arrival=303 *) output reg Q,
 219              input C, CE, D, R);
 220   parameter [0:0] INIT = 1'b0;
 221   parameter [0:0] IS_C_INVERTED = 1'b0;
 222   parameter [0:0] IS_D_INVERTED = 1'b0;
 223   parameter [0:0] IS_R_INVERTED = 1'b0;
 224   initial Q <= INIT;
 225   generate case (|IS_C_INVERTED)
 226     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 227     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 228   endcase endgenerate
 229 endmodule
 230
 231 module FDSE ((* abc_arrival=303 *) output reg Q,
 232              input C, CE, D, S);
 233   parameter [0:0] INIT = 1'b1;
 234   parameter [0:0] IS_C_INVERTED = 1'b0;
 235   parameter [0:0] IS_D_INVERTED = 1'b0;
 236   parameter [0:0] IS_S_INVERTED = 1'b0;
 237   initial Q <= INIT;
 238   generate case (|IS_C_INVERTED)
 239     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 240     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 241   endcase endgenerate
 242 endmodule
 243
 244 module FDCE ((* abc_arrival=303 *) output reg Q,
 245              input C, CE, D, CLR);
 246   parameter [0:0] INIT = 1'b0;
 247   parameter [0:0] IS_C_INVERTED = 1'b0;
 248   parameter [0:0] IS_D_INVERTED = 1'b0;
 249   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 250   initial Q <= INIT;
 251   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 252     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 253     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 254     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 255     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 256   endcase endgenerate
 257 endmodule
 258
 259 module FDPE ((* abc_arrival=303 *) output reg Q,
 260              input C, CE, D, PRE);
 261   parameter [0:0] INIT = 1'b1;
 262   parameter [0:0] IS_C_INVERTED = 1'b0;
 263   parameter [0:0] IS_D_INVERTED = 1'b0;
 264   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 265   initial Q <= INIT;
 266   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 267     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 268     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 269     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 270     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 271   endcase endgenerate
 272 endmodule
 273
 274 module FDRE_1 ((* abc_arrival=303 *) output reg Q,
 275                input C, CE, D, R);
 276   parameter [0:0] INIT = 1'b0;
 277   initial Q <= INIT;
 278   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 279 endmodule
 280
 281 module FDSE_1 ((* abc_arrival=303 *) output reg Q,
 282                input C, CE, D, S);
 283   parameter [0:0] INIT = 1'b1;
 284   initial Q <= INIT;
 285   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 286 endmodule
 287
 288 module FDCE_1 ((* abc_arrival=303 *) output reg Q,
 289                input C, CE, D, CLR);
 290   parameter [0:0] INIT = 1'b0;
 291   initial Q <= INIT;
 292   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 293 endmodule
 294
 295 module FDPE_1 ((* abc_arrival=303 *) output reg Q,
 296                input C, CE, D, PRE);
 297   parameter [0:0] INIT = 1'b1;
 298   initial Q <= INIT;
 299   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 300 endmodule
 301
 302 module RAM32X1D (
 303   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 304   (* abc_arrival=1153 *)
 305   output DPO, SPO,
 306   input  D,
 307   input  WCLK,
 308   input  WE,
 309   input  A0, A1, A2, A3, A4,
 310   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 311 );
 312   parameter INIT = 32'h0;
 313   parameter IS_WCLK_INVERTED = 1'b0;
 314   wire [4:0] a = {A4, A3, A2, A1, A0};
 315   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 316   reg [31:0] mem = INIT;
 317   assign SPO = mem[a];
 318   assign DPO = mem[dpra];
 319   wire clk = WCLK ^ IS_WCLK_INVERTED;
 320   always @(posedge clk) if (WE) mem[a] <= D;
 321 endmodule
 322
 323 module RAM64X1D (
 324   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 325   (* abc_arrival=1153 *)
 326   output DPO, SPO,
 327   input  D,
 328   input  WCLK,
 329   input  WE,
 330   input  A0, A1, A2, A3, A4, A5,
 331   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 332 );
 333   parameter INIT = 64'h0;
 334   parameter IS_WCLK_INVERTED = 1'b0;
 335   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 336   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 337   reg [63:0] mem = INIT;
 338   assign SPO = mem[a];
 339   assign DPO = mem[dpra];
 340   wire clk = WCLK ^ IS_WCLK_INVERTED;
 341   always @(posedge clk) if (WE) mem[a] <= D;
 342 endmodule
 343
 344 module RAM128X1D (
 345   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 346   (* abc_arrival=1153 *)
 347   output DPO, SPO,
 348   input        D,
 349   input        WCLK,
 350   input        WE,
 351   input  [6:0] A, DPRA
 352 );
 353   parameter INIT = 128'h0;
 354   parameter IS_WCLK_INVERTED = 1'b0;
 355   reg [127:0] mem = INIT;
 356   assign SPO = mem[A];
 357   assign DPO = mem[DPRA];
 358   wire clk = WCLK ^ IS_WCLK_INVERTED;
 359   always @(posedge clk) if (WE) mem[A] <= D;
 360 endmodule
 361
 362 module SRL16E (
 363   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
 364   (* abc_arrival=1472 *) output Q,
 365   input A0, A1, A2, A3, CE, CLK, D
 366 );
 367   parameter [15:0] INIT = 16'h0000;
 368   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 369
 370   reg [15:0] r = INIT;
 371   assign Q = r[{A3,A2,A1,A0}];
 372   generate
 373     if (IS_CLK_INVERTED) begin
 374       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 375     end
 376     else
 377         always @(posedge CLK) if (CE) r <= { r[14:0], D };
 378   endgenerate
 379 endmodule
 380
 381 module SRLC32E (
 382   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
 383   (* abc_arrival=1472 *) output Q,
 384   (* abc_arrival=1114 *) output Q31,
 385   input [4:0] A,
 386   input CE, CLK, D
 387 );
 388   parameter [31:0] INIT = 32'h00000000;
 389   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 390
 391   reg [31:0] r = INIT;
 392   assign Q31 = r[31];
 393   assign Q = r[A];
 394   generate
 395     if (IS_CLK_INVERTED) begin
 396       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 397     end
 398     else
 399       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 400   endgenerate
 401 endmodule