techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(output O, input I);
  33   parameter IOSTANDARD = "default";
  34   parameter IBUF_LOW_PWR = 0;
  35   assign O = I;
  36 endmodule
  37
  38 module OBUF(output O, input I);
  39   parameter IOSTANDARD = "default";
  40   parameter DRIVE = 12;
  41   parameter SLEW = "SLOW";
  42   assign O = I;
  43 endmodule
  44
  45 module BUFG(output O, input I);
  46   assign O = I;
  47 endmodule
  48
  49 module BUFGCTRL(
  50     output O,
  51     input I0, input I1,
  52     input S0, input S1,
  53     input CE0, input CE1,
  54     input IGNORE0, input IGNORE1);
  55
  56 parameter [0:0] INIT_OUT = 1'b0;
  57 parameter PRESELECT_I0 = "FALSE";
  58 parameter PRESELECT_I1 = "FALSE";
  59 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  60 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  61 parameter [0:0] IS_S0_INVERTED = 1'b0;
  62 parameter [0:0] IS_S1_INVERTED = 1'b0;
  63 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  64 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  65
  66 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  67 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  68 wire S0_true = (S0 ^ IS_S0_INVERTED);
  69 wire S1_true = (S1 ^ IS_S1_INVERTED);
  70
  71 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  72
  73 endmodule
  74
  75 module BUFHCE(output O, input I, input CE);
  76
  77 parameter [0:0] INIT_OUT = 1'b0;
  78 parameter CE_TYPE = "SYNC";
  79 parameter [0:0] IS_CE_INVERTED = 1'b0;
  80
  81 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  82
  83 endmodule
  84
  85 // module OBUFT(output O, input I, T);
  86 //   assign O = T ? 1'bz : I;
  87 // endmodule
  88
  89 // module IOBUF(inout IO, output O, input I, T);
  90 //   assign O = IO, IO = T ? 1'bz : I;
  91 // endmodule
  92
  93 module INV(output O, input I);
  94   assign O = !I;
  95 endmodule
  96
  97 module LUT1(output O, input I0);
  98   parameter [1:0] INIT = 0;
  99   assign O = I0 ? INIT[1] : INIT[0];
 100 endmodule
 101
 102 module LUT2(output O, input I0, I1);
 103   parameter [3:0] INIT = 0;
 104   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 105   assign O = I0 ? s1[1] : s1[0];
 106 endmodule
 107
 108 module LUT3(output O, input I0, I1, I2);
 109   parameter [7:0] INIT = 0;
 110   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 111   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 112   assign O = I0 ? s1[1] : s1[0];
 113 endmodule
 114
 115 module LUT4(output O, input I0, I1, I2, I3);
 116   parameter [15:0] INIT = 0;
 117   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 118   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 119   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT5(output O, input I0, I1, I2, I3, I4);
 124   parameter [31:0] INIT = 0;
 125   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 126   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 127   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 128   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 129   assign O = I0 ? s1[1] : s1[0];
 130 endmodule
 131
 132 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 133   parameter [63:0] INIT = 0;
 134   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 135   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 136   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 137   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 138   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 139   assign O = I0 ? s1[1] : s1[0];
 140 endmodule
 141
 142 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 143   parameter [63:0] INIT = 0;
 144   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 145   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 146   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 147   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 148   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 149   assign O6 = I0 ? s1[1] : s1[0];
 150
 151   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 152   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 153   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 154   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 155   assign O5 = I0 ? s5_1[1] : s5_1[0];
 156 endmodule
 157
 158 module MUXCY(output O, input CI, DI, S);
 159   assign O = S ? CI : DI;
 160 endmodule
 161
 162 (* abc_box_id = 1, lib_whitebox *)
 163 module MUXF7(output O, input I0, I1, S);
 164   assign O = S ? I1 : I0;
 165 endmodule
 166
 167 (* abc_box_id = 2, lib_whitebox *)
 168 module MUXF8(output O, input I0, I1, S);
 169   assign O = S ? I1 : I0;
 170 endmodule
 171
 172 `ifdef _ABC
 173 (* abc_box_id = 3, lib_whitebox *)
 174 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
 175   assign O = S1 ? (S0 ? I3 : I2)
 176                 : (S0 ? I1 : I0);
 177 endmodule
 178 `endif
 179
 180 module XORCY(output O, input CI, LI);
 181   assign O = CI ^ LI;
 182 endmodule
 183
 184 (* abc_box_id = 4, lib_whitebox *)
 185 module CARRY4(
 186   (* abc_carry *)
 187   output [3:0] CO,
 188   output [3:0] O,
 189   (* abc_carry *)
 190   input        CI,
 191   input        CYINIT,
 192   input  [3:0] DI, S
 193 );
 194   assign O = S ^ {CO[2:0], CI | CYINIT};
 195   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 196   assign CO[1] = S[1] ? CO[0] : DI[1];
 197   assign CO[2] = S[2] ? CO[1] : DI[2];
 198   assign CO[3] = S[3] ? CO[2] : DI[3];
 199 endmodule
 200
 201 `ifdef _EXPLICIT_CARRY
 202
 203 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 204   parameter CYINIT_FABRIC = 0;
 205   wire CI_COMBINE;
 206   if(CYINIT_FABRIC) begin
 207     assign CI_COMBINE = CI_INIT;
 208   end else begin
 209     assign CI_COMBINE = CI;
 210   end
 211   assign CO_CHAIN = S ? CI_COMBINE : DI;
 212   assign CO_FABRIC = S ? CI_COMBINE : DI;
 213   assign O = S ^ CI_COMBINE;
 214 endmodule
 215
 216 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 217   assign CO_CHAIN = S ? CI : DI;
 218   assign CO_FABRIC = S ? CI : DI;
 219   assign O = S ^ CI;
 220 endmodule
 221
 222 `endif
 223
 224 module FDRE (output reg Q, input C, CE, D, R);
 225   parameter [0:0] INIT = 1'b0;
 226   parameter [0:0] IS_C_INVERTED = 1'b0;
 227   parameter [0:0] IS_D_INVERTED = 1'b0;
 228   parameter [0:0] IS_R_INVERTED = 1'b0;
 229   initial Q <= INIT;
 230   generate case (|IS_C_INVERTED)
 231     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 232     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 233   endcase endgenerate
 234 endmodule
 235
 236 module FDSE (output reg Q, input C, CE, D, S);
 237   parameter [0:0] INIT = 1'b1;
 238   parameter [0:0] IS_C_INVERTED = 1'b0;
 239   parameter [0:0] IS_D_INVERTED = 1'b0;
 240   parameter [0:0] IS_S_INVERTED = 1'b0;
 241   initial Q <= INIT;
 242   generate case (|IS_C_INVERTED)
 243     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 244     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 245   endcase endgenerate
 246 endmodule
 247
 248 module FDCE (output reg Q, input C, CE, D, CLR);
 249   parameter [0:0] INIT = 1'b0;
 250   parameter [0:0] IS_C_INVERTED = 1'b0;
 251   parameter [0:0] IS_D_INVERTED = 1'b0;
 252   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 253   initial Q <= INIT;
 254   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 255     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 256     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 257     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 258     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 259   endcase endgenerate
 260 endmodule
 261
 262 module FDPE (output reg Q, input C, CE, D, PRE);
 263   parameter [0:0] INIT = 1'b1;
 264   parameter [0:0] IS_C_INVERTED = 1'b0;
 265   parameter [0:0] IS_D_INVERTED = 1'b0;
 266   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 267   initial Q <= INIT;
 268   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 269     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 270     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 271     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 272     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 273   endcase endgenerate
 274 endmodule
 275
 276 module FDRE_1 (output reg Q, input C, CE, D, R);
 277   parameter [0:0] INIT = 1'b0;
 278   initial Q <= INIT;
 279   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 280 endmodule
 281
 282 module FDSE_1 (output reg Q, input C, CE, D, S);
 283   parameter [0:0] INIT = 1'b1;
 284   initial Q <= INIT;
 285   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 286 endmodule
 287
 288 module FDCE_1 (output reg Q, input C, CE, D, CLR);
 289   parameter [0:0] INIT = 1'b0;
 290   initial Q <= INIT;
 291   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 292 endmodule
 293
 294 module FDPE_1 (output reg Q, input C, CE, D, PRE);
 295   parameter [0:0] INIT = 1'b1;
 296   initial Q <= INIT;
 297   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 298 endmodule
 299
 300 (* abc_box_id = 5 *)
 301 module RAM32X1D (
 302   output DPO, SPO,
 303   (* abc_scc_break *)
 304   input  D,
 305   input  WCLK,
 306   (* abc_scc_break *)
 307   input  WE,
 308   input  A0, A1, A2, A3, A4,
 309   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 310 );
 311   parameter INIT = 32'h0;
 312   parameter IS_WCLK_INVERTED = 1'b0;
 313   wire [4:0] a = {A4, A3, A2, A1, A0};
 314   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 315   reg [31:0] mem = INIT;
 316   assign SPO = mem[a];
 317   assign DPO = mem[dpra];
 318   wire clk = WCLK ^ IS_WCLK_INVERTED;
 319   always @(posedge clk) if (WE) mem[a] <= D;
 320 endmodule
 321
 322 (* abc_box_id = 6 *)
 323 module RAM64X1D (
 324   output DPO, SPO,
 325   (* abc_scc_break *)
 326   input  D,
 327   input  WCLK,
 328   (* abc_scc_break *)
 329   input  WE,
 330   input  A0, A1, A2, A3, A4, A5,
 331   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 332 );
 333   parameter INIT = 64'h0;
 334   parameter IS_WCLK_INVERTED = 1'b0;
 335   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 336   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 337   reg [63:0] mem = INIT;
 338   assign SPO = mem[a];
 339   assign DPO = mem[dpra];
 340   wire clk = WCLK ^ IS_WCLK_INVERTED;
 341   always @(posedge clk) if (WE) mem[a] <= D;
 342 endmodule
 343
 344 (* abc_box_id = 7 *)
 345 module RAM128X1D (
 346   output       DPO, SPO,
 347   (* abc_scc_break *)
 348   input        D,
 349   input        WCLK,
 350   (* abc_scc_break *)
 351   input        WE,
 352   input  [6:0] A, DPRA
 353 );
 354   parameter INIT = 128'h0;
 355   parameter IS_WCLK_INVERTED = 1'b0;
 356   reg [127:0] mem = INIT;
 357   assign SPO = mem[A];
 358   assign DPO = mem[DPRA];
 359   wire clk = WCLK ^ IS_WCLK_INVERTED;
 360   always @(posedge clk) if (WE) mem[A] <= D;
 361 endmodule
 362
 363 module SRL16E (
 364   output Q,
 365   input A0, A1, A2, A3, CE, CLK, D
 366 );
 367   parameter [15:0] INIT = 16'h0000;
 368   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 369
 370   reg [15:0] r = INIT;
 371   assign Q = r[{A3,A2,A1,A0}];
 372   generate
 373     if (IS_CLK_INVERTED) begin
 374       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 375     end
 376     else
 377         always @(posedge CLK) if (CE) r <= { r[14:0], D };
 378   endgenerate
 379 endmodule
 380
 381 module SRLC32E (
 382   output Q,
 383   output Q31,
 384   input [4:0] A,
 385   input CE, CLK, D
 386 );
 387   parameter [31:0] INIT = 32'h00000000;
 388   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 389
 390   reg [31:0] r = INIT;
 391   assign Q31 = r[31];
 392   assign Q = r[A];
 393   generate
 394     if (IS_CLK_INVERTED) begin
 395       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 396     end
 397     else
 398       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 399   endgenerate
 400 endmodule