techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(output O, input I);
  33   parameter IOSTANDARD = "default";
  34   parameter IBUF_LOW_PWR = 0;
  35   assign O = I;
  36 endmodule
  37
  38 module OBUF(output O, input I);
  39   parameter IOSTANDARD = "default";
  40   parameter DRIVE = 12;
  41   parameter SLEW = "SLOW";
  42   assign O = I;
  43 endmodule
  44
  45 module BUFG(output O, input I);
  46   assign O = I;
  47 endmodule
  48
  49 module BUFGCTRL(
  50     output O,
  51     input I0, input I1,
  52     input S0, input S1,
  53     input CE0, input CE1,
  54     input IGNORE0, input IGNORE1);
  55
  56 parameter [0:0] INIT_OUT = 1'b0;
  57 parameter PRESELECT_I0 = "FALSE";
  58 parameter PRESELECT_I1 = "FALSE";
  59 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  60 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  61 parameter [0:0] IS_S0_INVERTED = 1'b0;
  62 parameter [0:0] IS_S1_INVERTED = 1'b0;
  63 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  64 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  65
  66 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  67 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  68 wire S0_true = (S0 ^ IS_S0_INVERTED);
  69 wire S1_true = (S1 ^ IS_S1_INVERTED);
  70
  71 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  72
  73 endmodule
  74
  75 module BUFHCE(output O, input I, input CE);
  76
  77 parameter [0:0] INIT_OUT = 1'b0;
  78 parameter CE_TYPE = "SYNC";
  79 parameter [0:0] IS_CE_INVERTED = 1'b0;
  80
  81 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  82
  83 endmodule
  84
  85 // module OBUFT(output O, input I, T);
  86 //   assign O = T ? 1'bz : I;
  87 // endmodule
  88
  89 // module IOBUF(inout IO, output O, input I, T);
  90 //   assign O = IO, IO = T ? 1'bz : I;
  91 // endmodule
  92
  93 module INV(output O, input I);
  94   assign O = !I;
  95 endmodule
  96
  97 module LUT1(output O, input I0);
  98   parameter [1:0] INIT = 0;
  99   assign O = I0 ? INIT[1] : INIT[0];
 100 endmodule
 101
 102 module LUT2(output O, input I0, I1);
 103   parameter [3:0] INIT = 0;
 104   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 105   assign O = I0 ? s1[1] : s1[0];
 106 endmodule
 107
 108 module LUT3(output O, input I0, I1, I2);
 109   parameter [7:0] INIT = 0;
 110   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 111   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 112   assign O = I0 ? s1[1] : s1[0];
 113 endmodule
 114
 115 module LUT4(output O, input I0, I1, I2, I3);
 116   parameter [15:0] INIT = 0;
 117   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 118   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 119   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT5(output O, input I0, I1, I2, I3, I4);
 124   parameter [31:0] INIT = 0;
 125   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 126   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 127   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 128   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 129   assign O = I0 ? s1[1] : s1[0];
 130 endmodule
 131
 132 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 133   parameter [63:0] INIT = 0;
 134   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 135   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 136   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 137   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 138   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 139   assign O = I0 ? s1[1] : s1[0];
 140 endmodule
 141
 142 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 143   parameter [63:0] INIT = 0;
 144   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 145   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 146   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 147   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 148   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 149   assign O6 = I0 ? s1[1] : s1[0];
 150
 151   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 152   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 153   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 154   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 155   assign O5 = I0 ? s5_1[1] : s5_1[0];
 156 endmodule
 157
 158 module MUXCY(output O, input CI, DI, S);
 159   assign O = S ? CI : DI;
 160 endmodule
 161
 162 (* abc_box_id = 1 /*, lib_whitebox*/ *)
 163 module MUXF7(output O, input I0, I1, S);
 164   assign O = S ? I1 : I0;
 165 endmodule
 166
 167 (* abc_box_id = 2 /*, lib_whitebox*/ *)
 168 module MUXF8(output O, input I0, I1, S);
 169   assign O = S ? I1 : I0;
 170 endmodule
 171
 172 module XORCY(output O, input CI, LI);
 173   assign O = CI ^ LI;
 174 endmodule
 175
 176 (* abc_box_id = 3 /*, lib_whitebox*/ *)
 177 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
 178   assign O = S ^ {CO[2:0], CI | CYINIT};
 179   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 180   assign CO[1] = S[1] ? CO[0] : DI[1];
 181   assign CO[2] = S[2] ? CO[1] : DI[2];
 182   assign CO[3] = S[3] ? CO[2] : DI[3];
 183 endmodule
 184
 185 `ifdef _EXPLICIT_CARRY
 186
 187 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 188   parameter CYINIT_FABRIC = 0;
 189   wire CI_COMBINE;
 190   if(CYINIT_FABRIC) begin
 191     assign CI_COMBINE = CI_INIT;
 192   end else begin
 193     assign CI_COMBINE = CI;
 194   end
 195   assign CO_CHAIN = S ? CI_COMBINE : DI;
 196   assign CO_FABRIC = S ? CI_COMBINE : DI;
 197   assign O = S ^ CI_COMBINE;
 198 endmodule
 199
 200 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 201   assign CO_CHAIN = S ? CI : DI;
 202   assign CO_FABRIC = S ? CI : DI;
 203   assign O = S ^ CI;
 204 endmodule
 205
 206 `endif
 207
 208 module FDRE ((* abc_flop_q *) output reg Q, input C, CE, input D, R);
 209   parameter [0:0] INIT = 1'b0;
 210   parameter [0:0] IS_C_INVERTED = 1'b0;
 211   parameter [0:0] IS_D_INVERTED = 1'b0;
 212   parameter [0:0] IS_R_INVERTED = 1'b0;
 213   initial Q <= INIT;
 214   generate case (|IS_C_INVERTED)
 215     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 216     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 217   endcase endgenerate
 218 endmodule
 219
 220 module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
 221   parameter [0:0] INIT = 1'b0;
 222   parameter [0:0] IS_C_INVERTED = 1'b0;
 223   parameter [0:0] IS_D_INVERTED = 1'b0;
 224   parameter [0:0] IS_S_INVERTED = 1'b0;
 225   initial Q <= INIT;
 226   generate case (|IS_C_INVERTED)
 227     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 228     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 229   endcase endgenerate
 230 endmodule
 231
 232 module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
 233   parameter [0:0] INIT = 1'b0;
 234   parameter [0:0] IS_C_INVERTED = 1'b0;
 235   parameter [0:0] IS_D_INVERTED = 1'b0;
 236   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 237   initial Q <= INIT;
 238   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 239     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 240     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 241     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 242     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 243   endcase endgenerate
 244 endmodule
 245
 246 module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
 247   parameter [0:0] INIT = 1'b0;
 248   parameter [0:0] IS_C_INVERTED = 1'b0;
 249   parameter [0:0] IS_D_INVERTED = 1'b0;
 250   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 251   initial Q <= INIT;
 252   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 253     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 254     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 255     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 256     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 257   endcase endgenerate
 258 endmodule
 259
 260 module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
 261   parameter [0:0] INIT = 1'b0;
 262   initial Q <= INIT;
 263   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 264 endmodule
 265
 266 module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
 267   parameter [0:0] INIT = 1'b1;
 268   initial Q <= INIT;
 269   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 270 endmodule
 271
 272 module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
 273   parameter [0:0] INIT = 1'b0;
 274   initial Q <= INIT;
 275   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 276 endmodule
 277
 278 module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
 279   parameter [0:0] INIT = 1'b1;
 280   initial Q <= INIT;
 281   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 282 endmodule
 283
 284 (* abc_box_id = 4 /*, lib_whitebox*/ *)
 285 module RAM64X1D (
 286   output DPO, SPO,
 287   input  D, WCLK, WE,
 288   input  A0, A1, A2, A3, A4, A5,
 289   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 290 );
 291   parameter INIT = 64'h0;
 292   parameter IS_WCLK_INVERTED = 1'b0;
 293   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 294   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 295   reg [63:0] mem = INIT;
 296   assign SPO = mem[a];
 297   assign DPO = mem[dpra];
 298 `ifndef _ABC
 299   wire clk = WCLK ^ IS_WCLK_INVERTED;
 300   always @(posedge clk) if (WE) mem[a] <= D;
 301 `endif
 302 endmodule
 303
 304 (* abc_box_id = 5 /*, lib_whitebox*/ *)
 305 module RAM128X1D (
 306   output       DPO, SPO,
 307   input        D, WCLK, WE,
 308   input  [6:0] A, DPRA
 309 );
 310   parameter INIT = 128'h0;
 311   parameter IS_WCLK_INVERTED = 1'b0;
 312   reg [127:0] mem = INIT;
 313   assign SPO = mem[A];
 314   assign DPO = mem[DPRA];
 315 `ifndef _ABC
 316   wire clk = WCLK ^ IS_WCLK_INVERTED;
 317   always @(posedge clk) if (WE) mem[A] <= D;
 318 `endif
 319 endmodule
 320
 321 module SRL16E (
 322   (* abc_flop_q *) output Q,
 323   input A0, A1, A2, A3, CE, CLK, D
 324 );
 325   parameter [15:0] INIT = 16'h0000;
 326   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 327
 328   reg [15:0] r = INIT;
 329   assign Q = r[{A3,A2,A1,A0}];
 330   generate
 331     if (IS_CLK_INVERTED) begin
 332       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 333     end
 334     else
 335         always @(posedge CLK) if (CE) r <= { r[14:0], D };
 336   endgenerate
 337 endmodule
 338
 339 module SRLC32E (
 340   (* abc_flop_q *) output Q,
 341   output Q31,
 342   input [4:0] A,
 343   input CE, CLK, D
 344 );
 345   parameter [31:0] INIT = 32'h00000000;
 346   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 347
 348   reg [31:0] r = INIT;
 349   assign Q31 = r[31];
 350   assign Q = r[A];
 351   generate
 352     if (IS_CLK_INVERTED) begin
 353       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 354     end
 355     else
 356       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 357   endgenerate
 358 endmodule