techlibs/xilinx/cells_sim.v

   1
   2 // See Xilinx UG953 and UG474 for a description of the cell types below.
   3 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
   4 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
   5
   6 module VCC(output P);
   7   assign P = 1;
   8 endmodule
   9
  10 module GND(output G);
  11   assign G = 0;
  12 endmodule
  13
  14 module IBUF(output O, input I);
  15   assign O = I;
  16 endmodule
  17
  18 module OBUF(output O, input I);
  19   assign O = I;
  20 endmodule
  21
  22 module BUFG(output O, input I);
  23   assign O = I;
  24 endmodule
  25
  26 // module OBUFT(output O, input I, T);
  27 //   assign O = T ? 1'bz : I;
  28 // endmodule
  29
  30 // module IOBUF(inout IO, output O, input I, T);
  31 //   assign O = IO, IO = T ? 1'bz : I;
  32 // endmodule
  33
  34 module INV(output O, input I);
  35   assign O = !I;
  36 endmodule
  37
  38 module LUT1(output O, input I0);
  39   parameter [1:0] INIT = 0;
  40   assign O = I0 ? INIT[1] : INIT[0];
  41 endmodule
  42
  43 module LUT2(output O, input I0, I1);
  44   parameter [3:0] INIT = 0;
  45   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
  46   assign O = I0 ? s1[1] : s1[0];
  47 endmodule
  48
  49 module LUT3(output O, input I0, I1, I2);
  50   parameter [7:0] INIT = 0;
  51   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
  52   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  53   assign O = I0 ? s1[1] : s1[0];
  54 endmodule
  55
  56 module LUT4(output O, input I0, I1, I2, I3);
  57   parameter [15:0] INIT = 0;
  58   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
  59   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  60   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  61   assign O = I0 ? s1[1] : s1[0];
  62 endmodule
  63
  64 module LUT5(output O, input I0, I1, I2, I3, I4);
  65   parameter [31:0] INIT = 0;
  66   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
  67   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  68   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  69   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  70   assign O = I0 ? s1[1] : s1[0];
  71 endmodule
  72
  73 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
  74   parameter [63:0] INIT = 0;
  75   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
  76   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
  77   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  78   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  79   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  80   assign O = I0 ? s1[1] : s1[0];
  81 endmodule
  82
  83 module MUXCY(output O, input CI, DI, S);
  84   assign O = S ? CI : DI;
  85 endmodule
  86
  87 module MUXF7(output O, input I0, I1, S);
  88   assign O = S ? I1 : I0;
  89 endmodule
  90
  91 module MUXF8(output O, input I0, I1, S);
  92   assign O = S ? I1 : I0;
  93 endmodule
  94
  95 module XORCY(output O, input CI, LI);
  96   assign O = CI ^ LI;
  97 endmodule
  98
  99 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
 100   assign O = S ^ {CO[2:0], CI | CYINIT};
 101   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 102   assign CO[1] = S[1] ? CO[0] : DI[1];
 103   assign CO[2] = S[2] ? CO[1] : DI[2];
 104   assign CO[3] = S[3] ? CO[2] : DI[3];
 105 endmodule
 106
 107 module FDRE (output reg Q, input C, CE, D, R);
 108   parameter [0:0] INIT = 1'b0;
 109   parameter [0:0] IS_C_INVERTED = 1'b0;
 110   parameter [0:0] IS_D_INVERTED = 1'b0;
 111   parameter [0:0] IS_R_INVERTED = 1'b0;
 112   initial Q <= INIT;
 113   generate case (|IS_C_INVERTED)
 114     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 115     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 116   endcase endgenerate
 117 endmodule
 118
 119 module FDSE (output reg Q, input C, CE, D, S);
 120   parameter [0:0] INIT = 1'b0;
 121   parameter [0:0] IS_C_INVERTED = 1'b0;
 122   parameter [0:0] IS_D_INVERTED = 1'b0;
 123   parameter [0:0] IS_S_INVERTED = 1'b0;
 124   initial Q <= INIT;
 125   generate case (|IS_C_INVERTED)
 126     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 127     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 128   endcase endgenerate
 129 endmodule
 130
 131 module FDCE (output reg Q, input C, CE, D, CLR);
 132   parameter [0:0] INIT = 1'b0;
 133   parameter [0:0] IS_C_INVERTED = 1'b0;
 134   parameter [0:0] IS_D_INVERTED = 1'b0;
 135   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 136   initial Q <= INIT;
 137   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 138     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 139     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 140     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 141     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 142   endcase endgenerate
 143 endmodule
 144
 145 module FDPE (output reg Q, input C, CE, D, PRE);
 146   parameter [0:0] INIT = 1'b0;
 147   parameter [0:0] IS_C_INVERTED = 1'b0;
 148   parameter [0:0] IS_D_INVERTED = 1'b0;
 149   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 150   initial Q <= INIT;
 151   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 152     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 153     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 154     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 155     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 156   endcase endgenerate
 157 endmodule
 158
 159 module RAM64X1D (
 160   output DPO, SPO,
 161   input  D, WCLK, WE,
 162   input  A0, A1, A2, A3, A4, A5,
 163   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 164 );
 165   parameter INIT = 64'h0;
 166   parameter IS_WCLK_INVERTED = 1'b0;
 167   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 168   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 169   reg [63:0] mem = INIT;
 170   assign SPO = mem[a];
 171   assign DPO = mem[dpra];
 172   wire clk = WCLK ^ IS_WCLK_INVERTED;
 173   always @(posedge clk) if (WE) mem[a] <= D;
 174 endmodule
 175
 176 module RAM128X1D (
 177   output       DPO, SPO,
 178   input        D, WCLK, WE,
 179   input  [6:0] A, DPRA
 180 );
 181   parameter INIT = 128'h0;
 182   parameter IS_WCLK_INVERTED = 1'b0;
 183   reg [127:0] mem = INIT;
 184   assign SPO = mem[A];
 185   assign DPO = mem[DPRA];
 186   wire clk = WCLK ^ IS_WCLK_INVERTED;
 187   always @(posedge clk) if (WE) mem[A] <= D;
 188 endmodule