techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(
  33     output O,
  34     (* iopad_external_pin *)
  35     input I);
  36   parameter IOSTANDARD = "default";
  37   parameter IBUF_LOW_PWR = 0;
  38   assign O = I;
  39 endmodule
  40
  41 module OBUF(
  42     (* iopad_external_pin *)
  43     output O,
  44     input I);
  45   parameter IOSTANDARD = "default";
  46   parameter DRIVE = 12;
  47   parameter SLEW = "SLOW";
  48   assign O = I;
  49 endmodule
  50
  51 module BUFG(
  52     (* clkbuf_driver *)
  53     output O,
  54     input I);
  55
  56   assign O = I;
  57 endmodule
  58
  59 module BUFGCTRL(
  60     (* clkbuf_driver *)
  61     output O,
  62     input I0, input I1,
  63     input S0, input S1,
  64     input CE0, input CE1,
  65     input IGNORE0, input IGNORE1);
  66
  67 parameter [0:0] INIT_OUT = 1'b0;
  68 parameter PRESELECT_I0 = "FALSE";
  69 parameter PRESELECT_I1 = "FALSE";
  70 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  71 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  72 parameter [0:0] IS_S0_INVERTED = 1'b0;
  73 parameter [0:0] IS_S1_INVERTED = 1'b0;
  74 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  75 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  76
  77 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  78 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  79 wire S0_true = (S0 ^ IS_S0_INVERTED);
  80 wire S1_true = (S1 ^ IS_S1_INVERTED);
  81
  82 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  83
  84 endmodule
  85
  86 module BUFHCE(
  87     (* clkbuf_driver *)
  88     output O,
  89     input I,
  90     input CE);
  91
  92 parameter [0:0] INIT_OUT = 1'b0;
  93 parameter CE_TYPE = "SYNC";
  94 parameter [0:0] IS_CE_INVERTED = 1'b0;
  95
  96 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  97
  98 endmodule
  99
 100 // module OBUFT(output O, input I, T);
 101 //   assign O = T ? 1'bz : I;
 102 // endmodule
 103
 104 // module IOBUF(inout IO, output O, input I, T);
 105 //   assign O = IO, IO = T ? 1'bz : I;
 106 // endmodule
 107
 108 module INV(output O, input I);
 109   assign O = !I;
 110 endmodule
 111
 112 module LUT1(output O, input I0);
 113   parameter [1:0] INIT = 0;
 114   assign O = I0 ? INIT[1] : INIT[0];
 115 endmodule
 116
 117 module LUT2(output O, input I0, I1);
 118   parameter [3:0] INIT = 0;
 119   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT3(output O, input I0, I1, I2);
 124   parameter [7:0] INIT = 0;
 125   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 126   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 127   assign O = I0 ? s1[1] : s1[0];
 128 endmodule
 129
 130 module LUT4(output O, input I0, I1, I2, I3);
 131   parameter [15:0] INIT = 0;
 132   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 133   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 134   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 135   assign O = I0 ? s1[1] : s1[0];
 136 endmodule
 137
 138 module LUT5(output O, input I0, I1, I2, I3, I4);
 139   parameter [31:0] INIT = 0;
 140   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 141   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 142   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 143   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 144   assign O = I0 ? s1[1] : s1[0];
 145 endmodule
 146
 147 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 148   parameter [63:0] INIT = 0;
 149   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 150   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 151   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 152   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 153   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 154   assign O = I0 ? s1[1] : s1[0];
 155 endmodule
 156
 157 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 158   parameter [63:0] INIT = 0;
 159   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 160   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 161   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 162   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 163   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 164   assign O6 = I0 ? s1[1] : s1[0];
 165
 166   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 167   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 168   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 169   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 170   assign O5 = I0 ? s5_1[1] : s5_1[0];
 171 endmodule
 172
 173 module MUXCY(output O, input CI, DI, S);
 174   assign O = S ? CI : DI;
 175 endmodule
 176
 177 (* abc_box_id = 1, lib_whitebox *)
 178 module MUXF7(output O, input I0, I1, S);
 179   assign O = S ? I1 : I0;
 180 endmodule
 181
 182 (* abc_box_id = 2, lib_whitebox *)
 183 module MUXF8(output O, input I0, I1, S);
 184   assign O = S ? I1 : I0;
 185 endmodule
 186
 187 `ifdef _ABC
 188 (* abc_box_id = 3, lib_whitebox *)
 189 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
 190   assign O = S1 ? (S0 ? I3 : I2)
 191                 : (S0 ? I1 : I0);
 192 endmodule
 193 `endif
 194
 195 module XORCY(output O, input CI, LI);
 196   assign O = CI ^ LI;
 197 endmodule
 198
 199 (* abc_box_id = 4, lib_whitebox *)
 200 module CARRY4(
 201   (* abc_carry *)
 202   output [3:0] CO,
 203   output [3:0] O,
 204   (* abc_carry *)
 205   input        CI,
 206   input        CYINIT,
 207   input  [3:0] DI, S
 208 );
 209   assign O = S ^ {CO[2:0], CI | CYINIT};
 210   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 211   assign CO[1] = S[1] ? CO[0] : DI[1];
 212   assign CO[2] = S[2] ? CO[1] : DI[2];
 213   assign CO[3] = S[3] ? CO[2] : DI[3];
 214 endmodule
 215
 216 `ifdef _EXPLICIT_CARRY
 217
 218 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 219   parameter CYINIT_FABRIC = 0;
 220   wire CI_COMBINE;
 221   if(CYINIT_FABRIC) begin
 222     assign CI_COMBINE = CI_INIT;
 223   end else begin
 224     assign CI_COMBINE = CI;
 225   end
 226   assign CO_CHAIN = S ? CI_COMBINE : DI;
 227   assign CO_FABRIC = S ? CI_COMBINE : DI;
 228   assign O = S ^ CI_COMBINE;
 229 endmodule
 230
 231 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 232   assign CO_CHAIN = S ? CI : DI;
 233   assign CO_FABRIC = S ? CI : DI;
 234   assign O = S ^ CI;
 235 endmodule
 236
 237 `endif
 238
 239 module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
 240   parameter [0:0] INIT = 1'b0;
 241   parameter [0:0] IS_C_INVERTED = 1'b0;
 242   parameter [0:0] IS_D_INVERTED = 1'b0;
 243   parameter [0:0] IS_R_INVERTED = 1'b0;
 244   initial Q <= INIT;
 245   generate case (|IS_C_INVERTED)
 246     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 247     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 248   endcase endgenerate
 249 endmodule
 250
 251 module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
 252   parameter [0:0] INIT = 1'b1;
 253   parameter [0:0] IS_C_INVERTED = 1'b0;
 254   parameter [0:0] IS_D_INVERTED = 1'b0;
 255   parameter [0:0] IS_S_INVERTED = 1'b0;
 256   initial Q <= INIT;
 257   generate case (|IS_C_INVERTED)
 258     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 259     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 260   endcase endgenerate
 261 endmodule
 262
 263 module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
 264   parameter [0:0] INIT = 1'b0;
 265   parameter [0:0] IS_C_INVERTED = 1'b0;
 266   parameter [0:0] IS_D_INVERTED = 1'b0;
 267   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 268   initial Q <= INIT;
 269   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 270     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 271     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 272     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 273     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 274   endcase endgenerate
 275 endmodule
 276
 277 module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
 278   parameter [0:0] INIT = 1'b1;
 279   parameter [0:0] IS_C_INVERTED = 1'b0;
 280   parameter [0:0] IS_D_INVERTED = 1'b0;
 281   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 282   initial Q <= INIT;
 283   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 284     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 285     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 286     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 287     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 288   endcase endgenerate
 289 endmodule
 290
 291 module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
 292   parameter [0:0] INIT = 1'b0;
 293   initial Q <= INIT;
 294   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 295 endmodule
 296
 297 module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
 298   parameter [0:0] INIT = 1'b1;
 299   initial Q <= INIT;
 300   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 301 endmodule
 302
 303 module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
 304   parameter [0:0] INIT = 1'b0;
 305   initial Q <= INIT;
 306   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 307 endmodule
 308
 309 module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
 310   parameter [0:0] INIT = 1'b1;
 311   initial Q <= INIT;
 312   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 313 endmodule
 314
 315 (* abc_box_id = 5 *)
 316 module RAM32X1D (
 317   output DPO, SPO,
 318   (* abc_scc_break *)
 319   input  D,
 320   (* clkbuf_sink *)
 321   input  WCLK,
 322   (* abc_scc_break *)
 323   input  WE,
 324   input  A0, A1, A2, A3, A4,
 325   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 326 );
 327   parameter INIT = 32'h0;
 328   parameter IS_WCLK_INVERTED = 1'b0;
 329   wire [4:0] a = {A4, A3, A2, A1, A0};
 330   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 331   reg [31:0] mem = INIT;
 332   assign SPO = mem[a];
 333   assign DPO = mem[dpra];
 334   wire clk = WCLK ^ IS_WCLK_INVERTED;
 335   always @(posedge clk) if (WE) mem[a] <= D;
 336 endmodule
 337
 338 (* abc_box_id = 6 *)
 339 module RAM64X1D (
 340   output DPO, SPO,
 341   (* abc_scc_break *)
 342   input  D,
 343   (* clkbuf_sink *)
 344   input  WCLK,
 345   (* abc_scc_break *)
 346   input WE,
 347   input  A0, A1, A2, A3, A4, A5,
 348   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 349 );
 350   parameter INIT = 64'h0;
 351   parameter IS_WCLK_INVERTED = 1'b0;
 352   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 353   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 354   reg [63:0] mem = INIT;
 355   assign SPO = mem[a];
 356   assign DPO = mem[dpra];
 357   wire clk = WCLK ^ IS_WCLK_INVERTED;
 358   always @(posedge clk) if (WE) mem[a] <= D;
 359 endmodule
 360
 361 (* abc_box_id = 7 *)
 362 module RAM128X1D (
 363   output       DPO, SPO,
 364   (* abc_scc_break *)
 365   input        D,
 366   (* clkbuf_sink *)
 367   input        WCLK,
 368   (* abc_scc_break *)
 369   input        WE,
 370   input  [6:0] A, DPRA
 371 );
 372   parameter INIT = 128'h0;
 373   parameter IS_WCLK_INVERTED = 1'b0;
 374   reg [127:0] mem = INIT;
 375   assign SPO = mem[A];
 376   assign DPO = mem[DPRA];
 377   wire clk = WCLK ^ IS_WCLK_INVERTED;
 378   always @(posedge clk) if (WE) mem[A] <= D;
 379 endmodule
 380
 381 module SRL16E (
 382   output Q,
 383   (* clkbuf_sink *)
 384   input CLK,
 385   input A0, A1, A2, A3, CE, D
 386 );
 387   parameter [15:0] INIT = 16'h0000;
 388   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 389
 390   reg [15:0] r = INIT;
 391   assign Q = r[{A3,A2,A1,A0}];
 392   generate
 393     if (IS_CLK_INVERTED) begin
 394       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 395     end
 396     else
 397         always @(posedge CLK) if (CE) r <= { r[14:0], D };
 398   endgenerate
 399 endmodule
 400
 401 module SRLC32E (
 402   output Q,
 403   output Q31,
 404   input [4:0] A,
 405   (* clkbuf_sink *)
 406   input CLK,
 407   input CE, D
 408 );
 409   parameter [31:0] INIT = 32'h00000000;
 410   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 411
 412   reg [31:0] r = INIT;
 413   assign Q31 = r[31];
 414   assign Q = r[A];
 415   generate
 416     if (IS_CLK_INVERTED) begin
 417       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 418     end
 419     else
 420       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 421   endgenerate
 422 endmodule