techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(
  33     output O,
  34     (* iopad_external_pin *)
  35     input I);
  36   parameter IOSTANDARD = "default";
  37   parameter IBUF_LOW_PWR = 0;
  38   assign O = I;
  39 endmodule
  40
  41 module OBUF(
  42     (* iopad_external_pin *)
  43     output O,
  44     input I);
  45   parameter IOSTANDARD = "default";
  46   parameter DRIVE = 12;
  47   parameter SLEW = "SLOW";
  48   assign O = I;
  49 endmodule
  50
  51 module BUFG(
  52     (* clkbuf_driver *)
  53     output O,
  54     input I);
  55
  56   assign O = I;
  57 endmodule
  58
  59 module BUFGCTRL(
  60     (* clkbuf_driver *)
  61     output O,
  62     input I0, input I1,
  63     input S0, input S1,
  64     input CE0, input CE1,
  65     input IGNORE0, input IGNORE1);
  66
  67 parameter [0:0] INIT_OUT = 1'b0;
  68 parameter PRESELECT_I0 = "FALSE";
  69 parameter PRESELECT_I1 = "FALSE";
  70 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  71 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  72 parameter [0:0] IS_S0_INVERTED = 1'b0;
  73 parameter [0:0] IS_S1_INVERTED = 1'b0;
  74 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  75 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  76
  77 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  78 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  79 wire S0_true = (S0 ^ IS_S0_INVERTED);
  80 wire S1_true = (S1 ^ IS_S1_INVERTED);
  81
  82 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  83
  84 endmodule
  85
  86 module BUFHCE(
  87     (* clkbuf_driver *)
  88     output O,
  89     input I,
  90     input CE);
  91
  92 parameter [0:0] INIT_OUT = 1'b0;
  93 parameter CE_TYPE = "SYNC";
  94 parameter [0:0] IS_CE_INVERTED = 1'b0;
  95
  96 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  97
  98 endmodule
  99
 100 // module OBUFT(output O, input I, T);
 101 //   assign O = T ? 1'bz : I;
 102 // endmodule
 103
 104 // module IOBUF(inout IO, output O, input I, T);
 105 //   assign O = IO, IO = T ? 1'bz : I;
 106 // endmodule
 107
 108 module INV(output O, input I);
 109   assign O = !I;
 110 endmodule
 111
 112 module LUT1(output O, input I0);
 113   parameter [1:0] INIT = 0;
 114   assign O = I0 ? INIT[1] : INIT[0];
 115 endmodule
 116
 117 module LUT2(output O, input I0, I1);
 118   parameter [3:0] INIT = 0;
 119   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT3(output O, input I0, I1, I2);
 124   parameter [7:0] INIT = 0;
 125   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 126   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 127   assign O = I0 ? s1[1] : s1[0];
 128 endmodule
 129
 130 module LUT4(output O, input I0, I1, I2, I3);
 131   parameter [15:0] INIT = 0;
 132   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 133   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 134   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 135   assign O = I0 ? s1[1] : s1[0];
 136 endmodule
 137
 138 module LUT5(output O, input I0, I1, I2, I3, I4);
 139   parameter [31:0] INIT = 0;
 140   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 141   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 142   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 143   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 144   assign O = I0 ? s1[1] : s1[0];
 145 endmodule
 146
 147 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 148   parameter [63:0] INIT = 0;
 149   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 150   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 151   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 152   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 153   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 154   assign O = I0 ? s1[1] : s1[0];
 155 endmodule
 156
 157 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 158   parameter [63:0] INIT = 0;
 159   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 160   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 161   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 162   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 163   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 164   assign O6 = I0 ? s1[1] : s1[0];
 165
 166   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 167   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 168   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 169   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 170   assign O5 = I0 ? s5_1[1] : s5_1[0];
 171 endmodule
 172
 173 module MUXCY(output O, input CI, DI, S);
 174   assign O = S ? CI : DI;
 175 endmodule
 176
 177 (* abc_box_id = 1, lib_whitebox *)
 178 module MUXF7(output O, input I0, I1, S);
 179   assign O = S ? I1 : I0;
 180 endmodule
 181
 182 (* abc_box_id = 2, lib_whitebox *)
 183 module MUXF8(output O, input I0, I1, S);
 184   assign O = S ? I1 : I0;
 185 endmodule
 186
 187 `ifdef _ABC
 188 (* abc_box_id = 3, lib_whitebox *)
 189 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
 190   assign O = S1 ? (S0 ? I3 : I2)
 191                 : (S0 ? I1 : I0);
 192 endmodule
 193 `endif
 194
 195 module XORCY(output O, input CI, LI);
 196   assign O = CI ^ LI;
 197 endmodule
 198
 199 (* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
 200 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
 201   assign O = S ^ {CO[2:0], CI | CYINIT};
 202   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 203   assign CO[1] = S[1] ? CO[0] : DI[1];
 204   assign CO[2] = S[2] ? CO[1] : DI[2];
 205   assign CO[3] = S[3] ? CO[2] : DI[3];
 206 endmodule
 207
 208 `ifdef _EXPLICIT_CARRY
 209
 210 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 211   parameter CYINIT_FABRIC = 0;
 212   wire CI_COMBINE;
 213   if(CYINIT_FABRIC) begin
 214     assign CI_COMBINE = CI_INIT;
 215   end else begin
 216     assign CI_COMBINE = CI;
 217   end
 218   assign CO_CHAIN = S ? CI_COMBINE : DI;
 219   assign CO_FABRIC = S ? CI_COMBINE : DI;
 220   assign O = S ^ CI_COMBINE;
 221 endmodule
 222
 223 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 224   assign CO_CHAIN = S ? CI : DI;
 225   assign CO_FABRIC = S ? CI : DI;
 226   assign O = S ^ CI;
 227 endmodule
 228
 229 `endif
 230
 231 module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
 232   parameter [0:0] INIT = 1'b0;
 233   parameter [0:0] IS_C_INVERTED = 1'b0;
 234   parameter [0:0] IS_D_INVERTED = 1'b0;
 235   parameter [0:0] IS_R_INVERTED = 1'b0;
 236   initial Q <= INIT;
 237   generate case (|IS_C_INVERTED)
 238     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 239     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 240   endcase endgenerate
 241 endmodule
 242
 243 module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
 244   parameter [0:0] INIT = 1'b1;
 245   parameter [0:0] IS_C_INVERTED = 1'b0;
 246   parameter [0:0] IS_D_INVERTED = 1'b0;
 247   parameter [0:0] IS_S_INVERTED = 1'b0;
 248   initial Q <= INIT;
 249   generate case (|IS_C_INVERTED)
 250     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 251     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 252   endcase endgenerate
 253 endmodule
 254
 255 module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
 256   parameter [0:0] INIT = 1'b0;
 257   parameter [0:0] IS_C_INVERTED = 1'b0;
 258   parameter [0:0] IS_D_INVERTED = 1'b0;
 259   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 260   initial Q <= INIT;
 261   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 262     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 263     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 264     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 265     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 266   endcase endgenerate
 267 endmodule
 268
 269 module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
 270   parameter [0:0] INIT = 1'b1;
 271   parameter [0:0] IS_C_INVERTED = 1'b0;
 272   parameter [0:0] IS_D_INVERTED = 1'b0;
 273   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 274   initial Q <= INIT;
 275   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 276     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 277     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 278     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 279     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 280   endcase endgenerate
 281 endmodule
 282
 283 module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
 284   parameter [0:0] INIT = 1'b0;
 285   initial Q <= INIT;
 286   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 287 endmodule
 288
 289 module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
 290   parameter [0:0] INIT = 1'b1;
 291   initial Q <= INIT;
 292   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 293 endmodule
 294
 295 module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
 296   parameter [0:0] INIT = 1'b0;
 297   initial Q <= INIT;
 298   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 299 endmodule
 300
 301 module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
 302   parameter [0:0] INIT = 1'b1;
 303   initial Q <= INIT;
 304   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 305 endmodule
 306
 307 (* abc_box_id = 5, abc_scc_break="D,WE" *)
 308 module RAM32X1D (
 309   output DPO, SPO,
 310   (* clkbuf_sink *)
 311   input  WCLK,
 312   input  D, WE,
 313   input  A0, A1, A2, A3, A4,
 314   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 315 );
 316   parameter INIT = 32'h0;
 317   parameter IS_WCLK_INVERTED = 1'b0;
 318   wire [4:0] a = {A4, A3, A2, A1, A0};
 319   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 320   reg [31:0] mem = INIT;
 321   assign SPO = mem[a];
 322   assign DPO = mem[dpra];
 323   wire clk = WCLK ^ IS_WCLK_INVERTED;
 324   always @(posedge clk) if (WE) mem[a] <= D;
 325 endmodule
 326
 327 (* abc_box_id = 6, abc_scc_break="D,WE" *)
 328 module RAM64X1D (
 329   output DPO, SPO,
 330   (* clkbuf_sink *)
 331   input  WCLK,
 332   input  D, WE,
 333   input  A0, A1, A2, A3, A4, A5,
 334   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 335 );
 336   parameter INIT = 64'h0;
 337   parameter IS_WCLK_INVERTED = 1'b0;
 338   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 339   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 340   reg [63:0] mem = INIT;
 341   assign SPO = mem[a];
 342   assign DPO = mem[dpra];
 343   wire clk = WCLK ^ IS_WCLK_INVERTED;
 344   always @(posedge clk) if (WE) mem[a] <= D;
 345 endmodule
 346
 347 (* abc_box_id = 7, abc_scc_break="D,WE" *)
 348 module RAM128X1D (
 349   output       DPO, SPO,
 350   input        D, WE,
 351   (* clkbuf_sink *)
 352   input        WCLK,
 353   input  [6:0] A, DPRA
 354 );
 355   parameter INIT = 128'h0;
 356   parameter IS_WCLK_INVERTED = 1'b0;
 357   reg [127:0] mem = INIT;
 358   assign SPO = mem[A];
 359   assign DPO = mem[DPRA];
 360   wire clk = WCLK ^ IS_WCLK_INVERTED;
 361   always @(posedge clk) if (WE) mem[A] <= D;
 362 endmodule
 363
 364 module SRL16E (
 365   output Q,
 366   (* clkbuf_sink *)
 367   input CLK,
 368   input A0, A1, A2, A3, CE, D
 369 );
 370   parameter [15:0] INIT = 16'h0000;
 371   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 372
 373   reg [15:0] r = INIT;
 374   assign Q = r[{A3,A2,A1,A0}];
 375   generate
 376     if (IS_CLK_INVERTED) begin
 377       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 378     end
 379     else
 380         always @(posedge CLK) if (CE) r <= { r[14:0], D };
 381   endgenerate
 382 endmodule
 383
 384 module SRLC32E (
 385   output Q,
 386   output Q31,
 387   input [4:0] A,
 388   (* clkbuf_sink *)
 389   input CLK,
 390   input CE, D
 391 );
 392   parameter [31:0] INIT = 32'h00000000;
 393   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 394
 395   reg [31:0] r = INIT;
 396   assign Q31 = r[31];
 397   assign Q = r[A];
 398   generate
 399     if (IS_CLK_INVERTED) begin
 400       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 401     end
 402     else
 403       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 404   endgenerate
 405 endmodule