techlibs/xilinx/cells_sim.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // See Xilinx UG953 and UG474 for a description of the cell types below.
  21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
  23
  24 module VCC(output P);
  25   assign P = 1;
  26 endmodule
  27
  28 module GND(output G);
  29   assign G = 0;
  30 endmodule
  31
  32 module IBUF(
  33     output O,
  34     (* iopad_external_pin *)
  35     input I);
  36   parameter IOSTANDARD = "default";
  37   parameter IBUF_LOW_PWR = 0;
  38   assign O = I;
  39 endmodule
  40
  41 module OBUF(
  42     (* iopad_external_pin *)
  43     output O,
  44     input I);
  45   parameter IOSTANDARD = "default";
  46   parameter DRIVE = 12;
  47   parameter SLEW = "SLOW";
  48   assign O = I;
  49 endmodule
  50
  51 module BUFG(
  52     (* clkbuf_driver *)
  53     output O,
  54     input I);
  55
  56   assign O = I;
  57 endmodule
  58
  59 module BUFGCTRL(
  60     (* clkbuf_driver *)
  61     output O,
  62     input I0, input I1,
  63     input S0, input S1,
  64     input CE0, input CE1,
  65     input IGNORE0, input IGNORE1);
  66
  67 parameter [0:0] INIT_OUT = 1'b0;
  68 parameter PRESELECT_I0 = "FALSE";
  69 parameter PRESELECT_I1 = "FALSE";
  70 parameter [0:0] IS_CE0_INVERTED = 1'b0;
  71 parameter [0:0] IS_CE1_INVERTED = 1'b0;
  72 parameter [0:0] IS_S0_INVERTED = 1'b0;
  73 parameter [0:0] IS_S1_INVERTED = 1'b0;
  74 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
  75 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
  76
  77 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
  78 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
  79 wire S0_true = (S0 ^ IS_S0_INVERTED);
  80 wire S1_true = (S1 ^ IS_S1_INVERTED);
  81
  82 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
  83
  84 endmodule
  85
  86 module BUFHCE(
  87     (* clkbuf_driver *)
  88     output O,
  89     input I,
  90     input CE);
  91
  92 parameter [0:0] INIT_OUT = 1'b0;
  93 parameter CE_TYPE = "SYNC";
  94 parameter [0:0] IS_CE_INVERTED = 1'b0;
  95
  96 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
  97
  98 endmodule
  99
 100 // module OBUFT(output O, input I, T);
 101 //   assign O = T ? 1'bz : I;
 102 // endmodule
 103
 104 // module IOBUF(inout IO, output O, input I, T);
 105 //   assign O = IO, IO = T ? 1'bz : I;
 106 // endmodule
 107
 108 module INV(output O, input I);
 109   assign O = !I;
 110 endmodule
 111
 112 module LUT1(output O, input I0);
 113   parameter [1:0] INIT = 0;
 114   assign O = I0 ? INIT[1] : INIT[0];
 115 endmodule
 116
 117 module LUT2(output O, input I0, I1);
 118   parameter [3:0] INIT = 0;
 119   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
 120   assign O = I0 ? s1[1] : s1[0];
 121 endmodule
 122
 123 module LUT3(output O, input I0, I1, I2);
 124   parameter [7:0] INIT = 0;
 125   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
 126   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 127   assign O = I0 ? s1[1] : s1[0];
 128 endmodule
 129
 130 module LUT4(output O, input I0, I1, I2, I3);
 131   parameter [15:0] INIT = 0;
 132   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
 133   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 134   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 135   assign O = I0 ? s1[1] : s1[0];
 136 endmodule
 137
 138 module LUT5(output O, input I0, I1, I2, I3, I4);
 139   parameter [31:0] INIT = 0;
 140   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
 141   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 142   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 143   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 144   assign O = I0 ? s1[1] : s1[0];
 145 endmodule
 146
 147 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
 148   parameter [63:0] INIT = 0;
 149   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 150   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 151   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 152   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 153   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 154   assign O = I0 ? s1[1] : s1[0];
 155 endmodule
 156
 157 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 158   parameter [63:0] INIT = 0;
 159   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
 160   wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
 161   wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
 162   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
 163   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
 164   assign O6 = I0 ? s1[1] : s1[0];
 165
 166   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
 167   wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
 168   wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
 169   wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
 170   assign O5 = I0 ? s5_1[1] : s5_1[0];
 171 endmodule
 172
 173 module MUXCY(output O, input CI, DI, S);
 174   assign O = S ? CI : DI;
 175 endmodule
 176
 177 (* abc_box_id = 1, lib_whitebox *)
 178 module MUXF7(output O, input I0, I1, S);
 179   assign O = S ? I1 : I0;
 180 endmodule
 181
 182 (* abc_box_id = 2, lib_whitebox *)
 183 module MUXF8(output O, input I0, I1, S);
 184   assign O = S ? I1 : I0;
 185 endmodule
 186
 187 module XORCY(output O, input CI, LI);
 188   assign O = CI ^ LI;
 189 endmodule
 190
 191 (* abc_box_id = 4, lib_whitebox *)
 192 module CARRY4(
 193   (* abc_carry *)
 194   output [3:0] CO,
 195   output [3:0] O,
 196   (* abc_carry *)
 197   input        CI,
 198   input        CYINIT,
 199   input  [3:0] DI, S
 200 );
 201   assign O = S ^ {CO[2:0], CI | CYINIT};
 202   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
 203   assign CO[1] = S[1] ? CO[0] : DI[1];
 204   assign CO[2] = S[2] ? CO[1] : DI[2];
 205   assign CO[3] = S[3] ? CO[2] : DI[3];
 206 endmodule
 207
 208 `ifdef _EXPLICIT_CARRY
 209
 210 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
 211   parameter CYINIT_FABRIC = 0;
 212   wire CI_COMBINE;
 213   if(CYINIT_FABRIC) begin
 214     assign CI_COMBINE = CI_INIT;
 215   end else begin
 216     assign CI_COMBINE = CI;
 217   end
 218   assign CO_CHAIN = S ? CI_COMBINE : DI;
 219   assign CO_FABRIC = S ? CI_COMBINE : DI;
 220   assign O = S ^ CI_COMBINE;
 221 endmodule
 222
 223 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
 224   assign CO_CHAIN = S ? CI : DI;
 225   assign CO_FABRIC = S ? CI : DI;
 226   assign O = S ^ CI;
 227 endmodule
 228
 229 `endif
 230
 231 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 232
 233 module FDRE (
 234   (* abc_arrival=303 *)
 235   output reg Q,
 236   (* clkbuf_sink *)
 237   input C,
 238   input CE, D, R
 239 );
 240   parameter [0:0] INIT = 1'b0;
 241   parameter [0:0] IS_C_INVERTED = 1'b0;
 242   parameter [0:0] IS_D_INVERTED = 1'b0;
 243   parameter [0:0] IS_R_INVERTED = 1'b0;
 244   initial Q <= INIT;
 245   generate case (|IS_C_INVERTED)
 246     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 247     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 248   endcase endgenerate
 249 endmodule
 250
 251 module FDSE (
 252   (* abc_arrival=303 *)
 253   output reg Q,
 254   (* clkbuf_sink *)
 255   input C,
 256   input CE, D, S
 257 );
 258   parameter [0:0] INIT = 1'b1;
 259   parameter [0:0] IS_C_INVERTED = 1'b0;
 260   parameter [0:0] IS_D_INVERTED = 1'b0;
 261   parameter [0:0] IS_S_INVERTED = 1'b0;
 262   initial Q <= INIT;
 263   generate case (|IS_C_INVERTED)
 264     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 265     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 266   endcase endgenerate
 267 endmodule
 268
 269 module FDCE (
 270   (* abc_arrival=303 *)
 271   output reg Q,
 272   (* clkbuf_sink *)
 273   input C,
 274   input CE, D, CLR
 275 );
 276   parameter [0:0] INIT = 1'b0;
 277   parameter [0:0] IS_C_INVERTED = 1'b0;
 278   parameter [0:0] IS_D_INVERTED = 1'b0;
 279   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 280   initial Q <= INIT;
 281   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 282     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 283     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 284     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 285     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
 286   endcase endgenerate
 287 endmodule
 288
 289 module FDPE (
 290   (* abc_arrival=303 *)
 291   output reg Q,
 292   (* clkbuf_sink *)
 293   input C,
 294   input CE, D, PRE
 295 );
 296   parameter [0:0] INIT = 1'b1;
 297   parameter [0:0] IS_C_INVERTED = 1'b0;
 298   parameter [0:0] IS_D_INVERTED = 1'b0;
 299   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 300   initial Q <= INIT;
 301   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
 302     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 303     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 304     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 305     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
 306   endcase endgenerate
 307 endmodule
 308
 309 module FDRE_1 (
 310   (* abc_arrival=303 *)
 311   output reg Q,
 312   (* clkbuf_sink *)
 313   input C,
 314   input CE, D, R
 315 );
 316   parameter [0:0] INIT = 1'b0;
 317   initial Q <= INIT;
 318   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 319 endmodule
 320
 321 module FDSE_1 (
 322   (* abc_arrival=303 *)
 323   output reg Q,
 324   (* clkbuf_sink *)
 325   input C,
 326   input CE, D, S
 327 );
 328   parameter [0:0] INIT = 1'b1;
 329   initial Q <= INIT;
 330   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 331 endmodule
 332
 333 module FDCE_1 (
 334   (* abc_arrival=303 *)
 335   output reg Q,
 336   (* clkbuf_sink *)
 337   input C,
 338   input CE, D, CLR
 339 );
 340   parameter [0:0] INIT = 1'b0;
 341   initial Q <= INIT;
 342   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 343 endmodule
 344
 345 module FDPE_1 (
 346   (* abc_arrival=303 *)
 347   output reg Q,
 348   (* clkbuf_sink *)
 349   input C,
 350   input CE, D, PRE
 351 );
 352   parameter [0:0] INIT = 1'b1;
 353   initial Q <= INIT;
 354   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 355 endmodule
 356
 357 module RAM32X1D (
 358   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 359   (* abc_arrival=1153 *)
 360   output DPO, SPO,
 361   input  D,
 362   (* clkbuf_sink *)
 363   input  WCLK,
 364   input  WE,
 365   input  A0, A1, A2, A3, A4,
 366   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 367 );
 368   parameter INIT = 32'h0;
 369   parameter IS_WCLK_INVERTED = 1'b0;
 370   wire [4:0] a = {A4, A3, A2, A1, A0};
 371   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 372   reg [31:0] mem = INIT;
 373   assign SPO = mem[a];
 374   assign DPO = mem[dpra];
 375   wire clk = WCLK ^ IS_WCLK_INVERTED;
 376   always @(posedge clk) if (WE) mem[a] <= D;
 377 endmodule
 378
 379 module RAM64X1D (
 380   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 381   (* abc_arrival=1153 *)
 382   output DPO, SPO,
 383   input  D,
 384   (* clkbuf_sink *)
 385   input  WCLK,
 386   input  WE,
 387   input  A0, A1, A2, A3, A4, A5,
 388   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 389 );
 390   parameter INIT = 64'h0;
 391   parameter IS_WCLK_INVERTED = 1'b0;
 392   wire [5:0] a = {A5, A4, A3, A2, A1, A0};
 393   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
 394   reg [63:0] mem = INIT;
 395   assign SPO = mem[a];
 396   assign DPO = mem[dpra];
 397   wire clk = WCLK ^ IS_WCLK_INVERTED;
 398   always @(posedge clk) if (WE) mem[a] <= D;
 399 endmodule
 400
 401 module RAM128X1D (
 402   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 403   (* abc_arrival=1153 *)
 404   output DPO, SPO,
 405   input        D,
 406   (* clkbuf_sink *)
 407   input        WCLK,
 408   input        WE,
 409   input  [6:0] A, DPRA
 410 );
 411   parameter INIT = 128'h0;
 412   parameter IS_WCLK_INVERTED = 1'b0;
 413   reg [127:0] mem = INIT;
 414   assign SPO = mem[A];
 415   assign DPO = mem[DPRA];
 416   wire clk = WCLK ^ IS_WCLK_INVERTED;
 417   always @(posedge clk) if (WE) mem[A] <= D;
 418 endmodule
 419
 420 module SRL16E (
 421   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
 422   (* abc_arrival=1472 *)
 423   output Q,
 424   input A0, A1, A2, A3, CE,
 425   (* clkbuf_sink *)
 426   input CLK,
 427   input D
 428 );
 429   parameter [15:0] INIT = 16'h0000;
 430   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 431
 432   reg [15:0] r = INIT;
 433   assign Q = r[{A3,A2,A1,A0}];
 434   generate
 435     if (IS_CLK_INVERTED) begin
 436       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 437     end
 438     else
 439       always @(posedge CLK) if (CE) r <= { r[14:0], D };
 440   endgenerate
 441 endmodule
 442
 443 module SRLC16E (
 444   output Q,
 445   output Q15,
 446   input A0, A1, A2, A3, CE,
 447   (* clkbuf_sink *)
 448   input CLK,
 449   input D
 450 );
 451   parameter [15:0] INIT = 16'h0000;
 452   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 453
 454   reg [15:0] r = INIT;
 455   assign Q15 = r[15];
 456   assign Q = r[{A3,A2,A1,A0}];
 457   generate
 458     if (IS_CLK_INVERTED) begin
 459       always @(negedge CLK) if (CE) r <= { r[14:0], D };
 460     end
 461     else
 462       always @(posedge CLK) if (CE) r <= { r[14:0], D };
 463   endgenerate
 464 endmodule
 465
 466 module SRLC32E (
 467   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
 468   (* abc_arrival=1472 *)
 469   output Q,
 470   (* abc_arrival=1114 *)
 471   output Q31,
 472   input [4:0] A,
 473   input CE,
 474   (* clkbuf_sink *)
 475   input CLK,
 476   input D
 477 );
 478   parameter [31:0] INIT = 32'h00000000;
 479   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 480
 481   reg [31:0] r = INIT;
 482   assign Q31 = r[31];
 483   assign Q = r[A];
 484   generate
 485     if (IS_CLK_INVERTED) begin
 486       always @(negedge CLK) if (CE) r <= { r[30:0], D };
 487     end
 488     else
 489       always @(posedge CLK) if (CE) r <= { r[30:0], D };
 490   endgenerate
 491 endmodule