2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // See Xilinx UG953 and UG474 for a description of the cell types below.
21 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
22 // http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
32 module IBUF(output O, input I);
33 parameter IOSTANDARD = "default";
34 parameter IBUF_LOW_PWR = 0;
38 module OBUF(output O, input I);
39 parameter IOSTANDARD = "default";
41 parameter SLEW = "SLOW";
45 module BUFG(output O, input I);
54 input IGNORE0, input IGNORE1);
56 parameter [0:0] INIT_OUT = 1'b0;
57 parameter PRESELECT_I0 = "FALSE";
58 parameter PRESELECT_I1 = "FALSE";
59 parameter [0:0] IS_CE0_INVERTED = 1'b0;
60 parameter [0:0] IS_CE1_INVERTED = 1'b0;
61 parameter [0:0] IS_S0_INVERTED = 1'b0;
62 parameter [0:0] IS_S1_INVERTED = 1'b0;
63 parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
64 parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
66 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
67 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
68 wire S0_true = (S0 ^ IS_S0_INVERTED);
69 wire S1_true = (S1 ^ IS_S1_INVERTED);
71 assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
75 module BUFHCE(output O, input I, input CE);
77 parameter [0:0] INIT_OUT = 1'b0;
78 parameter CE_TYPE = "SYNC";
79 parameter [0:0] IS_CE_INVERTED = 1'b0;
81 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
85 // module OBUFT(output O, input I, T);
86 // assign O = T ? 1'bz : I;
89 // module IOBUF(inout IO, output O, input I, T);
90 // assign O = IO, IO = T ? 1'bz : I;
93 module INV(output O, input I);
97 module LUT1(output O, input I0);
98 parameter [1:0] INIT = 0;
99 assign O = I0 ? INIT[1] : INIT[0];
102 module LUT2(output O, input I0, I1);
103 parameter [3:0] INIT = 0;
104 wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
105 assign O = I0 ? s1[1] : s1[0];
108 module LUT3(output O, input I0, I1, I2);
109 parameter [7:0] INIT = 0;
110 wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
111 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
112 assign O = I0 ? s1[1] : s1[0];
115 module LUT4(output O, input I0, I1, I2, I3);
116 parameter [15:0] INIT = 0;
117 wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
118 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
119 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
120 assign O = I0 ? s1[1] : s1[0];
123 module LUT5(output O, input I0, I1, I2, I3, I4);
124 parameter [31:0] INIT = 0;
125 wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
126 wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
127 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
128 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
129 assign O = I0 ? s1[1] : s1[0];
132 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
133 parameter [63:0] INIT = 0;
134 wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
135 wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
136 wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
137 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
138 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
139 assign O = I0 ? s1[1] : s1[0];
142 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
143 parameter [63:0] INIT = 0;
144 wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
145 wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
146 wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
147 wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
148 wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
149 assign O6 = I0 ? s1[1] : s1[0];
151 wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
152 wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
153 wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
154 wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
155 assign O5 = I0 ? s5_1[1] : s5_1[0];
158 module MUXCY(output O, input CI, DI, S);
159 assign O = S ? CI : DI;
162 (* abc_box_id = 1, lib_whitebox *)
163 module MUXF7(output O, input I0, I1, S);
164 assign O = S ? I1 : I0;
167 (* abc_box_id = 2, lib_whitebox *)
168 module MUXF8(output O, input I0, I1, S);
169 assign O = S ? I1 : I0;
173 (* abc_box_id = 3, lib_whitebox *)
174 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
175 assign O = S1 ? (S0 ? I3 : I2)
180 module XORCY(output O, input CI, LI);
184 (* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
185 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
186 assign O = S ^ {CO[2:0], CI | CYINIT};
187 assign CO[0] = S[0] ? CI | CYINIT : DI[0];
188 assign CO[1] = S[1] ? CO[0] : DI[1];
189 assign CO[2] = S[2] ? CO[1] : DI[2];
190 assign CO[3] = S[3] ? CO[2] : DI[3];
193 `ifdef _EXPLICIT_CARRY
195 module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
196 parameter CYINIT_FABRIC = 0;
198 if(CYINIT_FABRIC) begin
199 assign CI_COMBINE = CI_INIT;
201 assign CI_COMBINE = CI;
203 assign CO_CHAIN = S ? CI_COMBINE : DI;
204 assign CO_FABRIC = S ? CI_COMBINE : DI;
205 assign O = S ^ CI_COMBINE;
208 module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
209 assign CO_CHAIN = S ? CI : DI;
210 assign CO_FABRIC = S ? CI : DI;
216 module FDRE (output reg Q, input C, CE, D, R);
217 parameter [0:0] INIT = 1'b0;
218 parameter [0:0] IS_C_INVERTED = 1'b0;
219 parameter [0:0] IS_D_INVERTED = 1'b0;
220 parameter [0:0] IS_R_INVERTED = 1'b0;
222 generate case (|IS_C_INVERTED)
223 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
224 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
228 module FDSE (output reg Q, input C, CE, D, S);
229 parameter [0:0] INIT = 1'b1;
230 parameter [0:0] IS_C_INVERTED = 1'b0;
231 parameter [0:0] IS_D_INVERTED = 1'b0;
232 parameter [0:0] IS_S_INVERTED = 1'b0;
234 generate case (|IS_C_INVERTED)
235 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
236 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
240 module FDCE (output reg Q, input C, CE, D, CLR);
241 parameter [0:0] INIT = 1'b0;
242 parameter [0:0] IS_C_INVERTED = 1'b0;
243 parameter [0:0] IS_D_INVERTED = 1'b0;
244 parameter [0:0] IS_CLR_INVERTED = 1'b0;
246 generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
247 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
248 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
249 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
250 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
254 module FDPE (output reg Q, input C, CE, D, PRE);
255 parameter [0:0] INIT = 1'b1;
256 parameter [0:0] IS_C_INVERTED = 1'b0;
257 parameter [0:0] IS_D_INVERTED = 1'b0;
258 parameter [0:0] IS_PRE_INVERTED = 1'b0;
260 generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
261 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
262 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
263 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
264 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
268 module FDRE_1 (output reg Q, input C, CE, D, R);
269 parameter [0:0] INIT = 1'b0;
271 always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
274 module FDSE_1 (output reg Q, input C, CE, D, S);
275 parameter [0:0] INIT = 1'b1;
277 always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
280 module FDCE_1 (output reg Q, input C, CE, D, CLR);
281 parameter [0:0] INIT = 1'b0;
283 always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
286 module FDPE_1 (output reg Q, input C, CE, D, PRE);
287 parameter [0:0] INIT = 1'b1;
289 always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
292 (* abc_box_id = 5, abc_scc_break="D,WE" *)
296 input A0, A1, A2, A3, A4,
297 input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
299 parameter INIT = 32'h0;
300 parameter IS_WCLK_INVERTED = 1'b0;
301 wire [4:0] a = {A4, A3, A2, A1, A0};
302 wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
303 reg [31:0] mem = INIT;
305 assign DPO = mem[dpra];
306 wire clk = WCLK ^ IS_WCLK_INVERTED;
307 always @(posedge clk) if (WE) mem[a] <= D;
310 (* abc_box_id = 6, abc_scc_break="D,WE" *)
314 input A0, A1, A2, A3, A4, A5,
315 input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
317 parameter INIT = 64'h0;
318 parameter IS_WCLK_INVERTED = 1'b0;
319 wire [5:0] a = {A5, A4, A3, A2, A1, A0};
320 wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
321 reg [63:0] mem = INIT;
323 assign DPO = mem[dpra];
324 wire clk = WCLK ^ IS_WCLK_INVERTED;
325 always @(posedge clk) if (WE) mem[a] <= D;
328 (* abc_box_id = 7, abc_scc_break="D,WE" *)
334 parameter INIT = 128'h0;
335 parameter IS_WCLK_INVERTED = 1'b0;
336 reg [127:0] mem = INIT;
338 assign DPO = mem[DPRA];
339 wire clk = WCLK ^ IS_WCLK_INVERTED;
340 always @(posedge clk) if (WE) mem[A] <= D;
345 input A0, A1, A2, A3, CE, CLK, D
347 parameter [15:0] INIT = 16'h0000;
348 parameter [0:0] IS_CLK_INVERTED = 1'b0;
351 assign Q = r[{A3,A2,A1,A0}];
353 if (IS_CLK_INVERTED) begin
354 always @(negedge CLK) if (CE) r <= { r[14:0], D };
357 always @(posedge CLK) if (CE) r <= { r[14:0], D };
367 parameter [31:0] INIT = 32'h00000000;
368 parameter [0:0] IS_CLK_INVERTED = 1'b0;
374 if (IS_CLK_INVERTED) begin
375 always @(negedge CLK) if (CE) r <= { r[30:0], D };
378 always @(posedge CLK) if (CE) r <= { r[30:0], D };
385 output reg CARRYCASCOUT,
386 output reg [3:0] CARRYOUT,
387 output reg MULTSIGNOUT,
389 output reg signed [47:0] P,
390 output PATTERNBDETECT,
391 output PATTERNDETECT,
394 input signed [29:0] A,
397 input signed [17:0] B,
402 input [2:0] CARRYINSEL,
433 parameter integer ACASCREG = 1;
434 parameter integer ADREG = 1;
435 parameter integer ALUMODEREG = 1;
436 parameter integer AREG = 1;
437 parameter AUTORESET_PATDET = "NO_RESET";
438 parameter A_INPUT = "DIRECT";
439 parameter integer BCASCREG = 1;
440 parameter integer BREG = 1;
441 parameter B_INPUT = "DIRECT";
442 parameter integer CARRYINREG = 1;
443 parameter integer CARRYINSELREG = 1;
444 parameter integer CREG = 1;
445 parameter integer DREG = 1;
446 parameter integer INMODEREG = 1;
447 parameter integer MREG = 1;
448 parameter integer OPMODEREG = 1;
449 parameter integer PREG = 1;
450 parameter SEL_MASK = "MASK";
451 parameter SEL_PATTERN = "PATTERN";
452 parameter USE_DPORT = "FALSE";
453 parameter USE_MULT = "MULTIPLY";
454 parameter USE_PATTERN_DETECT = "NO_PATDET";
455 parameter USE_SIMD = "ONE48";
456 parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
457 parameter [47:0] PATTERN = 48'h000000000000;
458 parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
459 parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
460 parameter [0:0] IS_CLK_INVERTED = 1'b0;
461 parameter [4:0] IS_INMODE_INVERTED = 5'b0;
462 parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
466 if (ACASCREG != 0) $fatal(1, "Unsupported ACASCREG value");
467 if (ADREG != 0) $fatal(1, "Unsupported ADREG value");
468 if (ALUMODEREG != 0) $fatal(1, "Unsupported ALUMODEREG value");
469 if (AREG == 2) $fatal(1, "Unsupported AREG value");
470 if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
471 if (A_INPUT != "DIRECT") $fatal(1, "Unsupported A_INPUT value");
472 if (BCASCREG != 0) $fatal(1, "Unsupported BCASCREG value");
473 if (BREG == 2) $fatal(1, "Unsupported BREG value");
474 if (B_INPUT != "DIRECT") $fatal(1, "Unsupported B_INPUT value");
475 if (CARRYINREG != 0) $fatal(1, "Unsupported CARRYINREG value");
476 if (CARRYINSELREG != 0) $fatal(1, "Unsupported CARRYINSELREG value");
477 if (CREG != 0) $fatal(1, "Unsupported CREG value");
478 if (DREG != 0) $fatal(1, "Unsupported DREG value");
479 if (INMODEREG != 0) $fatal(1, "Unsupported INMODEREG value");
480 if (MREG != 0) $fatal(1, "Unsupported MREG value");
481 if (OPMODEREG != 0) $fatal(1, "Unsupported OPMODEREG value");
482 //if (PREG != 0) $fatal(1, "Unsupported PREG value");
483 if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
484 if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
485 if (USE_DPORT != "FALSE") $fatal(1, "Unsupported USE_DPORT value");
486 if (USE_MULT != "MULTIPLY") $fatal(1, "Unsupported USE_MULT value");
487 if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value");
488 if (USE_SIMD != "ONE48") $fatal(1, "Unsupported USE_SIMD value");
489 if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
490 if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value");
491 if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value");
492 if (IS_INMODE_INVERTED != 5'b0) $fatal(1, "Unsupported IS_INMODE_INVERTED value");
493 if (IS_OPMODE_INVERTED != 7'b0) $fatal(1, "Unsupported IS_OPMODE_INVERTED value");
497 wire signed [29:0] A_muxed;
498 wire signed [17:0] B_muxed;
501 if (A_INPUT == "CASCADE") assign A_muxed = ACIN;
502 else assign A_muxed = A;
504 if (B_INPUT == "CASCADE") assign B_muxed = BCIN;
505 else assign B_muxed = B;
508 reg signed [29:0] Ar1, Ar2;
509 reg signed [24:0] Dr;
510 reg signed [17:0] Br1, Br2;
511 reg signed [47:0] Cr;
515 reg [2:0] CARRYINSELr;
518 // Configurable A register
520 always @(posedge CLK)
525 if (CEA1) Ar1 <= A_muxed;
526 if (CEA2) Ar2 <= Ar1;
528 end else if (AREG == 1) begin
529 always @(posedge CLK)
534 if (CEA1) Ar1 <= A_muxed;
535 if (CEA2) Ar2 <= A_muxed;
538 always @* Ar1 <= A_muxed;
539 always @* Ar2 <= A_muxed;
542 // Configurable A register
544 always @(posedge CLK)
549 if (CEB1) Br1 <= B_muxed;
550 if (CEB2) Br2 <= Br1;
552 end else if (AREG == 1) begin
553 always @(posedge CLK)
558 if (CEB1) Br1 <= B_muxed;
559 if (CEB2) Br2 <= B_muxed;
562 always @* Br1 <= B_muxed;
563 always @* Br2 <= B_muxed;
567 if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= D; end
568 else always @* Cr <= C;
570 if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
571 else always @* Dr <= D;
574 if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end
575 else always @* INMODEr <= INMODE;
576 if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end
577 else always @* OPMODEr <= OPMODE;
578 if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end
579 else always @* ALUMODEr <= ALUMODE;
580 if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end
581 else always @* CARRYINSELr <= CARRYINSEL;
586 if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1;
587 else assign ACOUT = Ar2;
588 if (BCASCREG == 1 && BREG == 2) assign BCOUT = Br1;
589 else assign BCOUT = Br2;
592 // A/D input selection and pre-adder
593 wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2;
594 wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed;
595 wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0;
596 wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
597 reg signed [24:0] ADr;
600 if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end
601 else always @* ADr <= AD_result;
605 wire signed [24:0] A_MULT;
606 wire signed [17:0] B_MULT = INMODEr[4] ? Br1 : Br2;
608 if (USE_DPORT == "TRUE") assign A_MULT = ADr;
609 else assign A_MULT = Ar12_gated;
612 wire signed [42:0] M = A_MULT * B_MULT;
613 reg signed [42:0] Mr;
615 // Multiplier result register
617 if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= M; end
618 else always @* Mr <= M;
621 // X, Y and Z ALU inputs
622 reg signed [47:0] X, Y, Z;
628 2'b01: X = $signed(M);
630 if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
634 if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
636 2'b11: X = $signed({Ar2, Br2});
643 2'b01: Y = 48'b0; // FIXME: more accurate partial product modelling?
645 if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
647 2'b10: Y = {48{1'b1}};
658 if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
663 if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
664 if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
666 3'b101: Z = $signed(PCIN[47:17]);
667 3'b110: Z = $signed(P[47:17]);
674 wire alu_cin = 1'b0; // FIXME*
676 wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z;
677 wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv;
678 wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y);
680 wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz;
681 wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz;
683 wire [48:0] maj_xyz_simd_gated;
684 wire [3:0] int_carry_in, int_carry_out, ext_carry_out;
686 assign int_carry_in[0] = 1'b0;
689 if (USE_SIMD == "FOUR12") begin
690 assign maj_xyz_simd_gated = {
691 maj_xyz_gated[47:36],
692 1'b0, maj_xyz_gated[34:24],
693 1'b0, maj_xyz_gated[22:12],
694 1'b0, maj_xyz_gated[10:0],
697 assign int_carry_in[3:1] = 3'b000;
698 assign ext_carry_out = {
700 maj_xyz_gated[35] ^ int_carry_out[2],
701 maj_xyz_gated[23] ^ int_carry_out[1],
702 maj_xyz_gated[11] ^ int_carry_out[0]
704 end else if (USE_SIMD == "TWO24") begin
705 assign maj_xyz_simd_gated = {
706 maj_xyz_gated[47:24],
707 1'b0, maj_xyz_gated[22:0],
710 assign int_carry_in[3:1] = {int_carry_out[2], 1'b0, int_carry_out[0]};
711 assign ext_carry_out = {
714 maj_xyz_gated[23] ^ int_carry_out[1],
717 end else if (USE_SIMD == "FOUR48") begin
718 assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin};
719 assign int_carry_in[3:1] = int_carry_out[2:0];
720 assign ext_carry_out = {
727 for (i = 0; i < 4; i++)
728 assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]}
729 + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i];
732 wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum;
733 wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out;
734 wire CARRYCASCOUTd = ext_carry_out[3];
735 wire MULTSIGNOUTd = Mr[42];
739 if (CARRYINSEL != 3'b000) $fatal(1, "Unsupported CARRYINSEL value");
745 always @(posedge CLK)
749 CARRYCASCOUT <= 1'b0;
751 end else if (CEP) begin
753 CARRYOUT <= CARRYOUTd;
754 CARRYCASCOUT <= CARRYCASCOUTd;
755 MULTSIGNOUT <= MULTSIGNOUTd;
760 CARRYOUT = CARRYOUTd;
761 CARRYCASCOUT = CARRYCASCOUTd;
762 MULTSIGNOUT = MULTSIGNOUTd;