techlibs/xilinx/drams.txt

   1
   2 bram $__XILINX_RAM32X1D
   3   init 1
   4   abits 5
   5   dbits 1
   6   groups 2
   7   ports  1 1
   8   wrmode 0 1
   9   enable 0 1
  10   transp 0 0
  11   clocks 0 1
  12   clkpol 0 2
  13 endbram
  14
  15 bram $__XILINX_RAM64X1D
  16   init 1
  17   abits 6
  18   dbits 1
  19   groups 2
  20   ports  1 1
  21   wrmode 0 1
  22   enable 0 1
  23   transp 0 0
  24   clocks 0 1
  25   clkpol 0 2
  26 endbram
  27
  28 bram $__XILINX_RAM128X1D
  29   init 1
  30   abits 7
  31   dbits 1
  32   groups 2
  33   ports  1 1
  34   wrmode 0 1
  35   enable 0 1
  36   transp 0 0
  37   clocks 0 1
  38   clkpol 0 2
  39 endbram
  40
  41 match $__XILINX_RAM32X1D
  42   min bits 3
  43   min wports 1
  44   make_outreg
  45   or_next_if_better
  46 endmatch
  47
  48 match $__XILINX_RAM64X1D
  49   min bits 5
  50   min wports 1
  51   make_outreg
  52   or_next_if_better
  53 endmatch
  54
  55 match $__XILINX_RAM128X1D
  56   min bits 9
  57   min wports 1
  58   make_outreg
  59 endmatch
  60