techlibs/xilinx/dsp_map.v

   1 module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y);
   2         wire [47:0] P_48;
   3         DSP48E1 #(
   4                 // Disable all registers
   5                 .ACASCREG(0),
   6                 .ADREG(0),
   7                 .A_INPUT("DIRECT"),
   8                 .ALUMODEREG(0),
   9                 .AREG(0),
  10                 .BCASCREG(0),
  11                 .B_INPUT("DIRECT"),
  12                 .BREG(0),
  13                 .CARRYINREG(0),
  14                 .CARRYINSELREG(0),
  15                 .CREG(0),
  16                 .DREG(0),
  17                 .INMODEREG(0),
  18                 .MREG(0),
  19                 .OPMODEREG(0),
  20                 .PREG(0)
  21         ) _TECHMAP_REPLACE_ (
  22                 //Data path
  23                 .A({{5{A[24]}}, A}),
  24                 .B(B),
  25                 .C(48'b0),
  26                 .D(24'b0),
  27                 .P(P_48),
  28
  29                 .INMODE(4'b0000),
  30                 .ALUMODE(4'b0000),
  31                 .OPMODE(7'b000101),
  32                 .CARRYINSEL(3'b000),
  33
  34                 .ACIN(30'b0),
  35                 .BCIN(18'b0),
  36                 .PCIN(48'b0),
  37                 .CARRYIN(1'b0)
  38         );
  39         assign Y = P_48;
  40 endmodule