techlibs/xilinx/lut4_lutrams.txt

   1 bram $__XILINX_RAM16X1D
   2   init 1
   3   abits 4
   4   dbits 1
   5   groups 2
   6   ports  1 1
   7   wrmode 0 1
   8   enable 0 1
   9   transp 0 0
  10   clocks 0 1
  11   clkpol 0 2
  12 endbram
  13
  14
  15 match $__XILINX_RAM16X1D
  16   min bits 2
  17   min wports 1
  18   make_outreg
  19 endmatch