2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 // ============================================================================
34 LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
38 LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
39 .I0(A[0]), .I1(A[1]));
42 LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
43 .I0(A[0]), .I1(A[1]), .I2(A[2]));
46 LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
47 .I0(A[0]), .I1(A[1]), .I2(A[2]),
51 LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
52 .I0(A[0]), .I1(A[1]), .I2(A[2]),
53 .I3(A[3]), .I4(A[4]));
56 LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
57 .I0(A[0]), .I1(A[1]), .I2(A[2]),
58 .I3(A[3]), .I4(A[4]), .I5(A[5]));
62 LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
63 .I0(A[0]), .I1(A[1]), .I2(A[2]),
64 .I3(A[3]), .I4(A[4]), .I5(A[5]));
65 LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
66 .I0(A[0]), .I1(A[1]), .I2(A[2]),
67 .I3(A[3]), .I4(A[4]), .I5(A[5]));
68 MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
71 wire T0, T1, T2, T3, T4, T5;
72 LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
73 .I0(A[0]), .I1(A[1]), .I2(A[2]),
74 .I3(A[3]), .I4(A[4]), .I5(A[5]));
75 LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
76 .I0(A[0]), .I1(A[1]), .I2(A[2]),
77 .I3(A[3]), .I4(A[4]), .I5(A[5]));
78 LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
79 .I0(A[0]), .I1(A[1]), .I2(A[2]),
80 .I3(A[3]), .I4(A[4]), .I5(A[5]));
81 LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
82 .I0(A[0]), .I1(A[1]), .I2(A[2]),
83 .I3(A[3]), .I4(A[4]), .I5(A[5]));
84 MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
85 MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
86 MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
88 wire _TECHMAP_FAIL_ = 1;