techlibs/xilinx/lut_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // LUT mapping
  22
  23 `ifndef _NO_LUTS
  24
  25 module \$lut (A, Y);
  26   parameter WIDTH = 0;
  27   parameter LUT = 0;
  28
  29   input [WIDTH-1:0] A;
  30   output Y;
  31
  32   generate
  33     if (WIDTH == 1) begin
  34       LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  35         .I0(A[0]));
  36     end else
  37     if (WIDTH == 2) begin
  38       LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  39         .I0(A[0]), .I1(A[1]));
  40     end else
  41     if (WIDTH == 3) begin
  42       LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  43         .I0(A[0]), .I1(A[1]), .I2(A[2]));
  44     end else
  45     if (WIDTH == 4) begin
  46       LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  47         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  48         .I3(A[3]));
  49     end else
  50     if (WIDTH == 5) begin
  51       LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  52         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  53         .I3(A[3]), .I4(A[4]));
  54     end else
  55     if (WIDTH == 6) begin
  56       LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
  57         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  58         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  59     end else
  60     if (WIDTH == 7) begin
  61       wire T0, T1;
  62       LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
  63         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  64         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  65       LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
  66         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  67         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  68       MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
  69     end else
  70     if (WIDTH == 8) begin
  71       wire T0, T1, T2, T3, T4, T5;
  72       LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
  73         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  74         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  75       LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
  76         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  77         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  78       LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
  79         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  80         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  81       LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
  82         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  83         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  84       MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
  85       MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
  86       MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
  87     end else begin
  88       wire _TECHMAP_FAIL_ = 1;
  89     end
  90   endgenerate
  91 endmodule
  92
  93 `endif
  94