techlibs/xilinx/lut_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // LUT mapping
  22
  23 `ifndef _NO_LUTS
  24
  25 module \$lut (A, Y);
  26   parameter WIDTH = 0;
  27   parameter LUT = 0;
  28
  29   input [WIDTH-1:0] A;
  30   output Y;
  31
  32   // Need to swap input ordering, and fix init accordingly,
  33   // to match ABC's expectation of LUT inputs in non-decreasing
  34   // delay order
  35   function [WIDTH-1:0] permute_index;
  36       input [WIDTH-1:0] i;
  37       integer j;
  38       begin
  39           permute_index = 0;
  40           for (j = 0; j < WIDTH; j = j + 1)
  41               permute_index[WIDTH-1 - j] = i[j];
  42       end
  43   endfunction
  44
  45   function [2**WIDTH-1:0] permute_init;
  46       input [2**WIDTH-1:0] orig;
  47       integer i;
  48       begin
  49           permute_init = 0;
  50           for (i = 0; i < 2**WIDTH; i = i + 1)
  51               permute_init[i] = orig[permute_index(i)];
  52       end
  53   endfunction
  54
  55   parameter [2**WIDTH-1:0] P_LUT = permute_init(LUT);
  56
  57   generate
  58     if (WIDTH == 1) begin
  59       LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  60         .I0(A[0]));
  61     end else
  62     if (WIDTH == 2) begin
  63       LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  64         .I0(A[1]), .I1(A[0]));
  65     end else
  66     if (WIDTH == 3) begin
  67       LUT3 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  68         .I0(A[2]), .I1(A[1]), .I2(A[0]));
  69     end else
  70     if (WIDTH == 4) begin
  71       LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  72         .I0(A[3]), .I1(A[2]), .I2(A[1]),
  73         .I3(A[0]));
  74     end else
  75     if (WIDTH == 5) begin
  76       LUT5 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  77         .I0(A[4]), .I1(A[3]), .I2(A[2]),
  78         .I3(A[1]), .I4(A[0]));
  79     end else
  80     if (WIDTH == 6) begin
  81       LUT6 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  82         .I0(A[5]), .I1(A[4]), .I2(A[3]),
  83         .I3(A[2]), .I4(A[1]), .I5(A[0]));
  84     end else
  85     if (WIDTH == 7) begin
  86       wire T0, T1;
  87       LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
  88         .I0(A[6]), .I1(A[5]), .I2(A[4]),
  89         .I3(A[3]), .I4(A[2]), .I5(A[1]));
  90       LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
  91         .I0(A[6]), .I1(A[5]), .I2(A[4]),
  92         .I3(A[3]), .I4(A[2]), .I5(A[1]));
  93       MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[0]));
  94     end else
  95     if (WIDTH == 8) begin
  96       wire T0, T1, T2, T3, T4, T5;
  97       LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
  98         .I0(A[7]), .I1(A[6]), .I2(A[5]),
  99         .I3(A[4]), .I4(A[3]), .I5(A[2]));
 100       LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
 101         .I0(A[7]), .I1(A[6]), .I2(A[5]),
 102         .I3(A[4]), .I4(A[3]), .I5(A[2]));
 103       LUT6 #(.INIT(P_LUT[191:128])) fpga_lut_2 (.O(T2),
 104         .I0(A[7]), .I1(A[6]), .I2(A[5]),
 105         .I3(A[4]), .I4(A[3]), .I5(A[2]));
 106       LUT6 #(.INIT(P_LUT[255:192])) fpga_lut_3 (.O(T3),
 107         .I0(A[7]), .I1(A[6]), .I2(A[5]),
 108         .I3(A[4]), .I4(A[3]), .I5(A[2]));
 109       MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[1]));
 110       MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[1]));
 111       MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[0]));
 112     end else begin
 113       wire _TECHMAP_FAIL_ = 1;
 114     end
 115   endgenerate
 116 endmodule
 117
 118 `endif
 119