techlibs/xilinx/lut_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // ============================================================================
  21 // LUT mapping
  22
  23 `ifndef _NO_LUTS
  24
  25 module \$lut (A, Y);
  26   parameter WIDTH = 0;
  27   parameter LUT = 0;
  28
  29   input [WIDTH-1:0] A;
  30   output Y;
  31
  32   // Need to swap input ordering of wide LUTs, and fix init accordingly,
  33   // to match ABC's expectation of LUT inputs in non-decreasing
  34   // delay order
  35   function [WIDTH-1:0] permute_index;
  36       input [WIDTH-1:0] i;
  37       integer j;
  38       begin
  39           if (WIDTH == 7)
  40               permute_index = { i[5:0], i[6] };
  41           else if (WIDTH == 8)
  42               permute_index = { i[5:0], i[6], i[7] };
  43           else
  44               permute_index = i;
  45       end
  46   endfunction
  47
  48   function [2**WIDTH-1:0] permute_init;
  49       integer i;
  50       begin
  51           permute_init = 0;
  52           for (i = 0; i < 2**WIDTH; i = i + 1)
  53               permute_init[i] = LUT[permute_index(i)];
  54       end
  55   endfunction
  56
  57   parameter [2**WIDTH-1:0] P_LUT = permute_init();
  58
  59   generate
  60     if (WIDTH == 1) begin
  61       LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  62         .I0(A[0]));
  63     end else
  64     if (WIDTH == 2) begin
  65       LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  66         .I0(A[0]), .I1(A[1]));
  67     end else
  68     if (WIDTH == 3) begin
  69       LUT3 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  70         .I0(A[0]), .I1(A[1]), .I2(A[2]));
  71     end else
  72     if (WIDTH == 4) begin
  73       LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  74         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  75         .I3(A[3]));
  76     end else
  77     if (WIDTH == 5) begin
  78       LUT5 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  79         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  80         .I3(A[3]), .I4(A[4]));
  81     end else
  82     if (WIDTH == 6) begin
  83       LUT6 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
  84         .I0(A[0]), .I1(A[1]), .I2(A[2]),
  85         .I3(A[3]), .I4(A[4]), .I5(A[5]));
  86     end else
  87     if (WIDTH == 7) begin
  88       wire T0, T1;
  89       LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
  90         .I0(A[1]), .I1(A[2]), .I2(A[3]),
  91         .I3(A[4]), .I4(A[5]), .I5(A[6]));
  92       LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
  93         .I0(A[1]), .I1(A[2]), .I2(A[3]),
  94         .I3(A[4]), .I4(A[5]), .I5(A[6]));
  95       MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[0]));
  96     end else
  97     if (WIDTH == 8) begin
  98       wire T0, T1, T2, T3, T4, T5;
  99       LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
 100         .I0(A[2]), .I1(A[3]), .I2(A[4]),
 101         .I3(A[5]), .I4(A[6]), .I5(A[7]));
 102       LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
 103         .I0(A[2]), .I1(A[3]), .I2(A[4]),
 104         .I3(A[5]), .I4(A[6]), .I5(A[7]));
 105       LUT6 #(.INIT(P_LUT[191:128])) fpga_lut_2 (.O(T2),
 106         .I0(A[2]), .I1(A[3]), .I2(A[4]),
 107         .I3(A[5]), .I4(A[6]), .I5(A[7]));
 108       LUT6 #(.INIT(P_LUT[255:192])) fpga_lut_3 (.O(T3),
 109         .I0(A[2]), .I1(A[3]), .I2(A[4]),
 110         .I3(A[5]), .I4(A[6]), .I5(A[7]));
 111       MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[1]));
 112       MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[1]));
 113       MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[0]));
 114     end else begin
 115       wire _TECHMAP_FAIL_ = 1;
 116     end
 117   endgenerate
 118 endmodule
 119
 120 `endif
 121