2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 module \$shiftx (A, B, Y);
22 parameter A_SIGNED = 0;
23 parameter B_SIGNED = 0;
24 parameter A_WIDTH = 1;
25 parameter B_WIDTH = 1;
26 parameter Y_WIDTH = 1;
28 input [A_WIDTH-1:0] A;
29 input [B_WIDTH-1:0] B;
30 output [Y_WIDTH-1:0] Y;
32 parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
33 parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
37 // TODO: Check if this opt still necessary
39 if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
40 // Optimisation to remove B_SIGNED if sign bit of B is constant-0
41 \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
43 wire _TECHMAP_FAIL_ = 1;
45 else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
46 wire _TECHMAP_FAIL_ = 1;
49 \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));