techlibs/xilinx/mux_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // The purpose of these mapping rules is to allow preserve all (sufficiently
  22 // wide) $shiftx cells during 'techmap' so that they can be mapped to hard
  23 // resources, rather than being bit-blasted to gates during 'techmap'
  24 // execution
  25
  26 module \$shiftx (A, B, Y);
  27   parameter A_SIGNED = 0;
  28   parameter B_SIGNED = 0;
  29   parameter A_WIDTH = 1;
  30   parameter B_WIDTH = 1;
  31   parameter Y_WIDTH = 1;
  32
  33   input [A_WIDTH-1:0] A;
  34   input [B_WIDTH-1:0] B;
  35   output [Y_WIDTH-1:0] Y;
  36
  37   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
  38   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
  39
  40   generate
  41     if (B_SIGNED) begin
  42       if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
  43         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
  44         \$shiftx #(
  45           .A_SIGNED(A_SIGNED),
  46           .B_SIGNED(0),
  47           .A_WIDTH(A_WIDTH),
  48           .B_WIDTH(B_WIDTH-1'd1),
  49           .Y_WIDTH(Y_WIDTH)
  50         ) _TECHMAP_REPLACE_ (
  51           .A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
  52         );
  53       else
  54         wire _TECHMAP_FAIL_ = 1;
  55     end
  56     else begin
  57       if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
  58         wire _TECHMAP_FAIL_ = 1;
  59       else
  60         \$__XILINX_SHIFTX #(
  61           .A_SIGNED(A_SIGNED),
  62           .B_SIGNED(B_SIGNED),
  63           .A_WIDTH(A_WIDTH),
  64           .B_WIDTH(B_WIDTH),
  65           .Y_WIDTH(Y_WIDTH)
  66         ) _TECHMAP_REPLACE_ (
  67           .A(A), .B(B), .Y(Y)
  68         );
  69     end
  70   endgenerate
  71 endmodule