techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthXilinxPass : public ScriptPass
  29 {
  30         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_xilinx [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  39                 log("partly selected designs. At the moment this command creates netlists that are\n");
  40                 log("compatible with 7-Series Xilinx devices.\n");
  41                 log("\n");
  42                 log("    -top <module>\n");
  43                 log("        use the specified module as top module\n");
  44                 log("\n");
  45                 log("    -arch {xcup|xcu|xc7|xc6s}\n");
  46                 log("        run synthesis for the specified Xilinx architecture\n");
  47                 log("        default: xc7\n");
  48                 log("\n");
  49                 log("    -edif <file>\n");
  50                 log("        write the design to the specified edif file. writing of an output file\n");
  51                 log("        is omitted if this parameter is not specified.\n");
  52                 log("\n");
  53                 log("    -blif <file>\n");
  54                 log("        write the design to the specified BLIF file. writing of an output file\n");
  55                 log("        is omitted if this parameter is not specified.\n");
  56                 log("\n");
  57                 log("    -vpr\n");
  58                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  59                 log("        (this feature is experimental and incomplete)\n");
  60                 log("\n");
  61                 log("    -nocarry\n");
  62                 log("        disable inference of carry chains\n");
  63                 log("\n");
  64                 log("    -nobram\n");
  65                 log("        disable inference of block rams\n");
  66                 log("\n");
  67                 log("    -nodram\n");
  68                 log("        disable inference of distributed rams\n");
  69                 log("\n");
  70                 log("    -nosrl\n");
  71                 log("        disable inference of shift registers\n");
  72                 log("\n");
  73                 log("    -nomux\n");
  74                 log("        disable inference of wide multiplexers\n");
  75                 log("\n");
  76                 log("    -run <from_label>:<to_label>\n");
  77                 log("        only run the commands between the labels (see below). an empty\n");
  78                 log("        from label is synonymous to 'begin', and empty to label is\n");
  79                 log("        synonymous to the end of the command list.\n");
  80                 log("\n");
  81                 log("    -flatten\n");
  82                 log("        flatten design before synthesis\n");
  83                 log("\n");
  84                 log("    -retime\n");
  85                 log("        run 'abc' with -dff option\n");
  86                 log("\n");
  87                 log("    -abc9\n");
  88                 log("        use abc9 instead of abc\n");
  89                 log("\n");
  90                 log("\n");
  91                 log("The following commands are executed by this synthesis command:\n");
  92                 help_script();
  93                 log("\n");
  94         }
  95
  96         std::string top_opt, edif_file, blif_file, abc, arch;
  97         bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
  98
  99         void clear_flags() YS_OVERRIDE
 100         {
 101                 top_opt = "-auto-top";
 102                 edif_file.clear();
 103                 blif_file.clear();
 104                 abc = "abc";
 105                 flatten = false;
 106                 retime = false;
 107                 vpr = false;
 108                 nocarry = false;
 109                 nobram = false;
 110                 nodram = false;
 111                 nosrl = false;
 112                 nomux = false;
 113                 arch = "xc7";
 114         }
 115
 116         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 117         {
 118                 std::string run_from, run_to;
 119                 clear_flags();
 120
 121                 size_t argidx;
 122                 for (argidx = 1; argidx < args.size(); argidx++)
 123                 {
 124                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 125                                 top_opt = "-top " + args[++argidx];
 126                                 continue;
 127                         }
 128                         if (args[argidx] == "-arch" && argidx+1 < args.size()) {
 129                                 arch = args[++argidx];
 130                                 continue;
 131                         }
 132                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 133                                 edif_file = args[++argidx];
 134                                 continue;
 135                         }
 136                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 137                                 blif_file = args[++argidx];
 138                                 continue;
 139                         }
 140                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 141                                 size_t pos = args[argidx+1].find(':');
 142                                 if (pos == std::string::npos)
 143                                         break;
 144                                 run_from = args[++argidx].substr(0, pos);
 145                                 run_to = args[argidx].substr(pos+1);
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-flatten") {
 149                                 flatten = true;
 150                                 continue;
 151                         }
 152                         if (args[argidx] == "-retime") {
 153                                 retime = true;
 154                                 continue;
 155                         }
 156                         if (args[argidx] == "-vpr") {
 157                                 vpr = true;
 158                                 continue;
 159                         }
 160                         if (args[argidx] == "-nocarry") {
 161                                 nocarry = true;
 162                                 continue;
 163                         }
 164                         if (args[argidx] == "-nobram") {
 165                                 nobram = true;
 166                                 continue;
 167                         }
 168                         if (args[argidx] == "-nodram") {
 169                                 nodram = true;
 170                                 continue;
 171                         }
 172                         if (args[argidx] == "-nosrl") {
 173                                 nosrl = true;
 174                                 continue;
 175                         }
 176                         if (args[argidx] == "-nomux") {
 177                                 nomux = true;
 178                                 continue;
 179                         }
 180                         if (args[argidx] == "-abc9") {
 181                                 abc = "abc9";
 182                                 continue;
 183                         }
 184                         break;
 185                 }
 186                 extra_args(args, argidx, design);
 187
 188                 if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
 189                         log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
 190
 191                 if (!design->full_selection())
 192                         log_cmd_error("This command only operates on fully selected designs!\n");
 193
 194                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 195                 log_push();
 196
 197                 run_script(design, run_from, run_to);
 198
 199                 log_pop();
 200         }
 201
 202         void script() YS_OVERRIDE
 203         {
 204                 if (check_label("begin")) {
 205                         if (vpr)
 206                                 run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 207                         else
 208                                 run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
 209
 210                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 211
 212                         if (!nobram || help_mode)
 213                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 214
 215                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 216                 }
 217
 218                 if (check_label("flatten", "(with '-flatten' only)")) {
 219                         if (flatten || help_mode) {
 220                                 run("proc");
 221                                 run("flatten");
 222                         }
 223                 }
 224
 225                 if (check_label("coarse")) {
 226                         run("synth -run coarse");
 227
 228                         // shregmap -tech xilinx can cope with $shiftx and $mux
 229                         //   cells for identifying variable-length shift registers,
 230                         //   so attempt to convert $pmux-es to the former
 231                         // Also: wide multiplexer inference benefits from this too
 232                         if (!(nosrl && nomux) || help_mode)
 233                                 run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
 234
 235                         // Run a number of peephole optimisations, including one
 236                         //   that optimises $mul cells driving $shiftx's B input
 237                         //   and that aids wide mux analysis
 238                         run("peepopt");
 239                 }
 240
 241                 if (check_label("bram", "(skip if '-nobram')")) {
 242                         if (!nobram || help_mode) {
 243                                 run("memory_bram -rules +/xilinx/brams.txt");
 244                                 run("techmap -map +/xilinx/brams_map.v");
 245                         }
 246                 }
 247
 248                 if (check_label("dram", "(skip if '-nodram')")) {
 249                         if (!nodram || help_mode) {
 250                                 run("memory_bram -rules +/xilinx/drams.txt");
 251                                 run("techmap -map +/xilinx/drams_map.v");
 252                         }
 253                 }
 254
 255                 if (check_label("fine")) {
 256                         run("opt -fast -full");
 257                         run("memory_map");
 258                         run("dffsr2dff");
 259                         run("dff2dffe");
 260                         run("opt -full");
 261
 262                         if (!nosrl || help_mode) {
 263                                 // shregmap operates on bit-level flops, not word-level,
 264                                 //   so break those down here
 265                                 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 266                                 // shregmap with '-tech xilinx' infers variable length shift regs
 267                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 268                         }
 269
 270                         std::string techmap_files = " -map +/techmap.v";
 271                         if (help_mode)
 272                                         techmap_files += " [-map +/xilinx/mux_map.v]";
 273                         else if (!nomux)
 274                                         techmap_files += " -map +/xilinx/mux_map.v";
 275                         if (help_mode)
 276                                         techmap_files += " [-map +/xilinx/arith_map.v]";
 277                         else if (!nocarry) {
 278                                         techmap_files += " -map +/xilinx/arith_map.v";
 279                                         if (vpr)
 280                                                         techmap_files += " -D _EXPLICIT_CARRY";
 281                                         else if (abc == "abc9")
 282                                                         techmap_files += " -D _CLB_CARRY";
 283                         }
 284                         run("techmap " + techmap_files);
 285                         run("opt -fast");
 286                 }
 287
 288                 if (check_label("map_cells")) {
 289                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 290                         run("clean");
 291                 }
 292
 293                 if (check_label("map_luts")) {
 294                         if (abc == "abc9")
 295                                 run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
 296                         else if (help_mode)
 297                                 run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 298                         else
 299                                 run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 300                         run("clean");
 301
 302                         // This shregmap call infers fixed length shift registers after abc
 303                         //   has performed any necessary retiming
 304                         if (!nosrl || help_mode)
 305                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 306                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 307                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 308                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 309                         run("clean");
 310                 }
 311
 312                 if (check_label("check")) {
 313                         run("hierarchy -check");
 314                         run("stat -tech xilinx");
 315                         run("check -noinit");
 316                 }
 317
 318                 if (check_label("edif")) {
 319                         if (!edif_file.empty() || help_mode)
 320                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 321                 }
 322
 323                 if (check_label("blif")) {
 324                         if (!blif_file.empty() || help_mode)
 325                                 run(stringf("write_blif %s", edif_file.c_str()));
 326                 }
 327         }
 328 } SynthXilinxPass;
 329
 330 PRIVATE_NAMESPACE_END