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Add clock buffer insertion pass, improve iopadmap.
[yosys.git] / techlibs / xilinx / synth_xilinx.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 #define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
30 // to one LUT6 (instead of a LUT5 + LUT2)
31
32 struct SynthXilinxPass : public ScriptPass
33 {
34 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
35
36 void help() YS_OVERRIDE
37 {
38 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
39 log("\n");
40 log(" synth_xilinx [options]\n");
41 log("\n");
42 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
43 log("partly selected designs. At the moment this command creates netlists that are\n");
44 log("compatible with 7-Series Xilinx devices.\n");
45 log("\n");
46 log(" -top <module>\n");
47 log(" use the specified module as top module\n");
48 log("\n");
49 log(" -family {xcup|xcu|xc7|xc6s}\n");
50 log(" run synthesis for the specified Xilinx architecture\n");
51 log(" generate the synthesis netlist for the specified family.\n");
52 log(" default: xc7\n");
53 log("\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
57 log("\n");
58 log(" -blif <file>\n");
59 log(" write the design to the specified BLIF file. writing of an output file\n");
60 log(" is omitted if this parameter is not specified.\n");
61 log("\n");
62 log(" -vpr\n");
63 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
64 log(" (this feature is experimental and incomplete)\n");
65 log("\n");
66 log(" -ise\n");
67 log(" generate an output netlist suitable for ISE\n");
68 log("\n");
69 log(" -nobram\n");
70 log(" disable inference of block rams\n");
71 log("\n");
72 log(" -nodram\n");
73 log(" disable inference of distributed rams\n");
74 log("\n");
75 log(" -nosrl\n");
76 log(" disable inference of shift registers\n");
77 log("\n");
78 log(" -nocarry\n");
79 log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
80 log("\n");
81 log(" -nowidelut\n");
82 log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
83 log("\n");
84 log(" -iopads\n");
85 log(" perform I/O buffer insertion (selected automatically by -ise)\n");
86 log("\n");
87 log(" -noiopads\n");
88 log(" disable I/O buffer insertion (only useful with -ise)\n");
89 log("\n");
90 log(" -widemux <int>\n");
91 log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
92 log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
93 log(" default: 0 (no inference)\n");
94 log("\n");
95 log(" -run <from_label>:<to_label>\n");
96 log(" only run the commands between the labels (see below). an empty\n");
97 log(" from label is synonymous to 'begin', and empty to label is\n");
98 log(" synonymous to the end of the command list.\n");
99 log("\n");
100 log(" -flatten\n");
101 log(" flatten design before synthesis\n");
102 log("\n");
103 log(" -retime\n");
104 log(" run 'abc' with -dff option\n");
105 log("\n");
106 log(" -abc9\n");
107 log(" use new ABC9 flow (EXPERIMENTAL)\n");
108 log("\n");
109 log("\n");
110 log("The following commands are executed by this synthesis command:\n");
111 help_script();
112 log("\n");
113 }
114
115 std::string top_opt, edif_file, blif_file, family;
116 bool flatten, retime, vpr, ise, iopads, noiopads, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
117 int widemux;
118
119 void clear_flags() YS_OVERRIDE
120 {
121 top_opt = "-auto-top";
122 edif_file.clear();
123 blif_file.clear();
124 family = "xc7";
125 flatten = false;
126 retime = false;
127 vpr = false;
128 ise = false;
129 iopads = false;
130 noiopads = false;
131 nocarry = false;
132 nobram = false;
133 nodram = false;
134 nosrl = false;
135 nocarry = false;
136 nowidelut = false;
137 abc9 = false;
138 widemux = 0;
139 }
140
141 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
142 {
143 std::string run_from, run_to;
144 clear_flags();
145
146 size_t argidx;
147 for (argidx = 1; argidx < args.size(); argidx++)
148 {
149 if (args[argidx] == "-top" && argidx+1 < args.size()) {
150 top_opt = "-top " + args[++argidx];
151 continue;
152 }
153 if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
154 family = args[++argidx];
155 continue;
156 }
157 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
158 edif_file = args[++argidx];
159 continue;
160 }
161 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
162 blif_file = args[++argidx];
163 continue;
164 }
165 if (args[argidx] == "-run" && argidx+1 < args.size()) {
166 size_t pos = args[argidx+1].find(':');
167 if (pos == std::string::npos)
168 break;
169 run_from = args[++argidx].substr(0, pos);
170 run_to = args[argidx].substr(pos+1);
171 continue;
172 }
173 if (args[argidx] == "-flatten") {
174 flatten = true;
175 continue;
176 }
177 if (args[argidx] == "-retime") {
178 retime = true;
179 continue;
180 }
181 if (args[argidx] == "-nocarry") {
182 nocarry = true;
183 continue;
184 }
185 if (args[argidx] == "-nowidelut") {
186 nowidelut = true;
187 continue;
188 }
189 if (args[argidx] == "-vpr") {
190 vpr = true;
191 continue;
192 }
193 if (args[argidx] == "-ise") {
194 ise = true;
195 continue;
196 }
197 if (args[argidx] == "-iopads") {
198 iopads = true;
199 continue;
200 }
201 if (args[argidx] == "-noiopads") {
202 noiopads = true;
203 continue;
204 }
205 if (args[argidx] == "-nocarry") {
206 nocarry = true;
207 continue;
208 }
209 if (args[argidx] == "-nobram") {
210 nobram = true;
211 continue;
212 }
213 if (args[argidx] == "-nodram") {
214 nodram = true;
215 continue;
216 }
217 if (args[argidx] == "-nosrl") {
218 nosrl = true;
219 continue;
220 }
221 if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
222 widemux = atoi(args[++argidx].c_str());
223 continue;
224 }
225 if (args[argidx] == "-abc9") {
226 abc9 = true;
227 continue;
228 }
229 break;
230 }
231 extra_args(args, argidx, design);
232
233 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
234 log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
235
236 if (widemux != 0 && widemux < 2)
237 log_cmd_error("-widemux value must be 0 or >= 2.\n");
238
239 if (!design->full_selection())
240 log_cmd_error("This command only operates on fully selected designs!\n");
241
242 if (abc9 && retime)
243 log_cmd_error("-retime option not currently compatible with -abc9!\n");
244
245 log_header(design, "Executing SYNTH_XILINX pass.\n");
246 log_push();
247
248 run_script(design, run_from, run_to);
249
250 log_pop();
251 }
252
253 void script() YS_OVERRIDE
254 {
255 if (check_label("begin")) {
256 if (vpr)
257 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
258 else
259 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
260
261 run("read_verilog -lib +/xilinx/cells_xtra.v");
262
263 if (help_mode) {
264 run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
265 } else if (family == "xc6s") {
266 run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
267 } else if (family == "xc7") {
268 run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
269 }
270
271 run(stringf("hierarchy -check %s", top_opt.c_str()));
272 }
273
274 if (check_label("coarse")) {
275 run("proc");
276 if (help_mode || flatten)
277 run("flatten", "(if -flatten)");
278 run("opt_expr");
279 run("opt_clean");
280 run("check");
281 run("opt");
282 if (help_mode)
283 run("wreduce [-keepdc]", "(option for '-widemux')");
284 else
285 run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
286 run("peepopt");
287 run("opt_clean");
288
289 if (widemux > 0 || help_mode)
290 run("muxpack", " ('-widemux' only)");
291
292 // shregmap -tech xilinx can cope with $shiftx and $mux
293 // cells for identifying variable-length shift registers,
294 // so attempt to convert $pmux-es to the former
295 // Also: wide multiplexer inference benefits from this too
296 if (!(nosrl && widemux == 0) || help_mode) {
297 run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
298 run("clean", " (skip if '-nosrl' and '-widemux=0')");
299 }
300
301 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
302 run("alumacc");
303 run("share");
304 run("opt");
305 run("fsm");
306 run("opt -fast");
307 run("memory -nomap");
308 run("opt_clean");
309 }
310
311 if (check_label("bram", "(skip if '-nobram')")) {
312 if (help_mode) {
313 run("memory_bram -rules +/xilinx/{family}_brams.txt");
314 run("techmap -map +/xilinx/{family}_brams_map.v");
315 } else if (!nobram) {
316 if (family == "xc6s") {
317 run("memory_bram -rules +/xilinx/xc6s_brams.txt");
318 run("techmap -map +/xilinx/xc6s_brams_map.v");
319 } else if (family == "xc7") {
320 run("memory_bram -rules +/xilinx/xc7_brams.txt");
321 run("techmap -map +/xilinx/xc7_brams_map.v");
322 } else {
323 log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
324 }
325 }
326 }
327
328 if (check_label("dram", "(skip if '-nodram')")) {
329 if (!nodram || help_mode) {
330 run("memory_bram -rules +/xilinx/drams.txt");
331 run("techmap -map +/xilinx/drams_map.v");
332 }
333 }
334
335 if (check_label("fine")) {
336 if (widemux > 0)
337 run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
338 // performs less efficiently
339 else
340 run("opt -fast -full");
341 run("memory_map");
342 run("dffsr2dff");
343 run("dff2dffe");
344 if (help_mode) {
345 run("simplemap t:$mux", " ('-widemux' only)");
346 run("muxcover <internal options>, ('-widemux' only)");
347 }
348 else if (widemux > 0) {
349 run("simplemap t:$mux");
350 constexpr int cost_mux2 = 100;
351 std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
352 switch (widemux) {
353 case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
354 case 3:
355 case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
356 case 5:
357 case 6:
358 case 7:
359 case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
360 case 9:
361 case 10:
362 case 11:
363 case 12:
364 case 13:
365 case 14:
366 case 15:
367 default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
368 }
369 run("muxcover " + muxcover_args);
370 }
371 run("opt -full");
372
373 if (!nosrl || help_mode) {
374 // shregmap operates on bit-level flops, not word-level,
375 // so break those down here
376 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
377 // shregmap with '-tech xilinx' infers variable length shift regs
378 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
379 }
380
381 std::string techmap_args = " -map +/techmap.v";
382 if (help_mode)
383 techmap_args += " [-map +/xilinx/mux_map.v]";
384 else if (widemux > 0)
385 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
386 if (help_mode)
387 techmap_args += " [-map +/xilinx/arith_map.v]";
388 else if (!nocarry) {
389 techmap_args += " -map +/xilinx/arith_map.v";
390 if (vpr)
391 techmap_args += " -D _EXPLICIT_CARRY";
392 else if (abc9)
393 techmap_args += " -D _CLB_CARRY";
394 }
395 run("techmap " + techmap_args);
396 run("opt -fast");
397 }
398
399 if (check_label("map_cells")) {
400 std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
401 if (widemux > 0)
402 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
403 run("techmap " + techmap_args);
404 run("clean");
405 }
406
407 if (check_label("map_luts")) {
408 run("opt_expr -mux_undef");
409 if (help_mode)
410 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
411 else if (abc9) {
412 if (family != "xc7")
413 log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
414 if (nowidelut)
415 run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
416 else
417 run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
418 }
419 else {
420 if (nowidelut)
421 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
422 else
423 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
424 }
425 run("clean");
426
427 // This shregmap call infers fixed length shift registers after abc
428 // has performed any necessary retiming
429 if (!nosrl || help_mode)
430 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
431 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
432 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
433 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
434 run("clean");
435 }
436
437 if (check_label("finalize")) {
438 bool do_iopads = iopads || (ise && !noiopads);
439 if (help_mode || do_iopads)
440 run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(-inpad passed if '-iopads' or '-ise' and not '-noiopads')");
441 else
442 run("clkbufmap -buf BUFG O:I");
443
444 if (do_iopads)
445 run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopads' or '-ise' and not '-noiopads')");
446 }
447
448 if (check_label("check")) {
449 run("hierarchy -check");
450 run("stat -tech xilinx");
451 run("check -noinit");
452 }
453
454 if (check_label("edif")) {
455 if (!edif_file.empty() || help_mode)
456 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
457 }
458
459 if (check_label("blif")) {
460 if (!blif_file.empty() || help_mode)
461 run(stringf("write_blif %s", edif_file.c_str()));
462 }
463 }
464 } SynthXilinxPass;
465
466 PRIVATE_NAMESPACE_END