techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthXilinxPass : public ScriptPass
  29 {
  30         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_xilinx [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  39                 log("partly selected designs. At the moment this command creates netlists that are\n");
  40                 log("compatible with 7-Series Xilinx devices.\n");
  41                 log("\n");
  42                 log("    -top <module>\n");
  43                 log("        use the specified module as top module\n");
  44                 log("\n");
  45                 log("    -arch {xcup|xcu|xc7|xc6s}\n");
  46                 log("        run synthesis for the specified Xilinx architecture\n");
  47                 log("        default: xc7\n");
  48                 log("\n");
  49                 log("    -edif <file>\n");
  50                 log("        write the design to the specified edif file. writing of an output file\n");
  51                 log("        is omitted if this parameter is not specified.\n");
  52                 log("\n");
  53                 log("    -blif <file>\n");
  54                 log("        write the design to the specified BLIF file. writing of an output file\n");
  55                 log("        is omitted if this parameter is not specified.\n");
  56                 log("\n");
  57                 log("    -vpr\n");
  58                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  59                 log("        (this feature is experimental and incomplete)\n");
  60                 log("\n");
  61                 log("    -nobram\n");
  62                 log("        disable inference of block rams\n");
  63                 log("\n");
  64                 log("    -nodram\n");
  65                 log("        disable inference of distributed rams\n");
  66                 log("\n");
  67                 log("    -nosrl\n");
  68                 log("        disable inference of shift registers\n");
  69                 log("\n");
  70                 log("    -run <from_label>:<to_label>\n");
  71                 log("        only run the commands between the labels (see below). an empty\n");
  72                 log("        from label is synonymous to 'begin', and empty to label is\n");
  73                 log("        synonymous to the end of the command list.\n");
  74                 log("\n");
  75                 log("    -flatten\n");
  76                 log("        flatten design before synthesis\n");
  77                 log("\n");
  78                 log("    -retime\n");
  79                 log("        run 'abc' with -dff option\n");
  80                 log("\n");
  81                 log("\n");
  82                 log("The following commands are executed by this synthesis command:\n");
  83                 help_script();
  84                 log("\n");
  85         }
  86
  87         std::string top_opt, edif_file, blif_file, arch;
  88         bool flatten, retime, vpr, nobram, nodram, nosrl;
  89
  90         void clear_flags() YS_OVERRIDE
  91         {
  92                 top_opt = "-auto-top";
  93                 edif_file.clear();
  94                 blif_file.clear();
  95                 flatten = false;
  96                 retime = false;
  97                 vpr = false;
  98                 nobram = false;
  99                 nodram = false;
 100                 nosrl = false;
 101                 arch = "xc7";
 102         }
 103
 104         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 105         {
 106                 std::string run_from, run_to;
 107                 clear_flags();
 108
 109                 size_t argidx;
 110                 for (argidx = 1; argidx < args.size(); argidx++)
 111                 {
 112                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 113                                 top_opt = "-top " + args[++argidx];
 114                                 continue;
 115                         }
 116                         if (args[argidx] == "-arch" && argidx+1 < args.size()) {
 117                                 arch = args[++argidx];
 118                                 continue;
 119                         }
 120                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 121                                 edif_file = args[++argidx];
 122                                 continue;
 123                         }
 124                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 125                                 blif_file = args[++argidx];
 126                                 continue;
 127                         }
 128                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 129                                 size_t pos = args[argidx+1].find(':');
 130                                 if (pos == std::string::npos)
 131                                         break;
 132                                 run_from = args[++argidx].substr(0, pos);
 133                                 run_to = args[argidx].substr(pos+1);
 134                                 continue;
 135                         }
 136                         if (args[argidx] == "-flatten") {
 137                                 flatten = true;
 138                                 continue;
 139                         }
 140                         if (args[argidx] == "-retime") {
 141                                 retime = true;
 142                                 continue;
 143                         }
 144                         if (args[argidx] == "-vpr") {
 145                                 vpr = true;
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-nobram") {
 149                                 nobram = true;
 150                                 continue;
 151                         }
 152                         if (args[argidx] == "-nodram") {
 153                                 nodram = true;
 154                                 continue;
 155                         }
 156                         if (args[argidx] == "-nosrl") {
 157                                 nosrl = true;
 158                                 continue;
 159                         }
 160                         break;
 161                 }
 162                 extra_args(args, argidx, design);
 163
 164                 if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
 165                         log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
 166
 167                 if (!design->full_selection())
 168                         log_cmd_error("This command only operates on fully selected designs!\n");
 169
 170                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 171                 log_push();
 172
 173                 run_script(design, run_from, run_to);
 174
 175                 log_pop();
 176         }
 177
 178         void script() YS_OVERRIDE
 179         {
 180                 if (check_label("begin")) {
 181                         if (vpr)
 182                                 run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 183                         else
 184                                 run("read_verilog -lib +/xilinx/cells_sim.v");
 185
 186                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 187
 188                         if (!nobram || help_mode)
 189                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 190
 191                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 192                 }
 193
 194                 if (check_label("flatten", "(with '-flatten' only)")) {
 195                         if (flatten || help_mode) {
 196                                 run("proc");
 197                                 run("flatten");
 198                         }
 199                 }
 200
 201                 if (check_label("coarse")) {
 202                         run("synth -run coarse");
 203                 }
 204
 205                 if (check_label("bram", "(skip if '-nobram')")) {
 206                         if (!nobram || help_mode) {
 207                                 run("memory_bram -rules +/xilinx/brams.txt");
 208                                 run("techmap -map +/xilinx/brams_map.v");
 209                         }
 210                 }
 211
 212                 if (check_label("dram", "(skip if '-nodram')")) {
 213                         if (!nodram || help_mode) {
 214                                 run("memory_bram -rules +/xilinx/drams.txt");
 215                                 run("techmap -map +/xilinx/drams_map.v");
 216                         }
 217                 }
 218
 219                 if (check_label("fine")) {
 220                         // shregmap -tech xilinx can cope with $shiftx and $mux
 221                         //   cells for identifiying variable-length shift registers,
 222                         //   so attempt to convert $pmux-es to the former
 223                         if (!nosrl || help_mode)
 224                                 run("pmux2shiftx", "(skip if '-nosrl')");
 225
 226                         run("opt -fast -full");
 227                         run("memory_map");
 228                         run("dffsr2dff");
 229                         run("dff2dffe");
 230                         run("opt -full");
 231
 232                         if (!vpr || help_mode)
 233                                 run("techmap -map +/xilinx/arith_map.v");
 234                         else
 235                                 run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
 236
 237                         if (!nosrl || help_mode) {
 238                                 // shregmap operates on bit-level flops, not word-level,
 239                                 //   so break those down here
 240                                 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 241                                 // shregmap with '-tech xilinx' infers variable length shift regs
 242                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 243                         }
 244
 245                         run("techmap");
 246                         run("opt -fast");
 247                 }
 248
 249                 if (check_label("map_cells")) {
 250                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 251                         run("clean");
 252                 }
 253
 254                 if (check_label("map_luts")) {
 255                         if (help_mode)
 256                                 run("abc -luts 2:2,3,6:5,10,20 [-dff]");
 257                         else
 258                                 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 259                         run("clean");
 260                         // This shregmap call infers fixed length shift registers after abc
 261                         //   has performed any necessary retiming
 262                         if (!nosrl || help_mode)
 263                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 264                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 265                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 266                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 267                         run("clean");
 268                 }
 269
 270                 if (check_label("check")) {
 271                         run("hierarchy -check");
 272                         run("stat");
 273                         run("check -noinit");
 274                 }
 275
 276                 if (check_label("edif")) {
 277                         if (!edif_file.empty() || help_mode)
 278                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 279                 }
 280
 281                 if (check_label("blif")) {
 282                         if (!blif_file.empty() || help_mode)
 283                                 run(stringf("write_blif %s", edif_file.c_str()));
 284                 }
 285         }
 286 } SynthXilinxPass;
 287
 288 PRIVATE_NAMESPACE_END