b022972c925666186cb08922b124bf6dc7af545c
2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthXilinxPass
: public ScriptPass
30 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth_xilinx [options]\n");
38 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
39 log("partly selected designs. At the moment this command creates netlists that are\n");
40 log("compatible with 7-Series Xilinx devices.\n");
42 log(" -top <module>\n");
43 log(" use the specified module as top module\n");
45 log(" -arch {xcup|xcu|xc7|xc6s}\n");
46 log(" run synthesis for the specified Xilinx architecture\n");
47 log(" default: xc7\n");
49 log(" -edif <file>\n");
50 log(" write the design to the specified edif file. writing of an output file\n");
51 log(" is omitted if this parameter is not specified.\n");
53 log(" -blif <file>\n");
54 log(" write the design to the specified BLIF file. writing of an output file\n");
55 log(" is omitted if this parameter is not specified.\n");
58 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
59 log(" (this feature is experimental and incomplete)\n");
62 log(" disable inference of block rams\n");
65 log(" disable inference of distributed rams\n");
68 log(" disable inference of shift registers\n");
70 log(" -run <from_label>:<to_label>\n");
71 log(" only run the commands between the labels (see below). an empty\n");
72 log(" from label is synonymous to 'begin', and empty to label is\n");
73 log(" synonymous to the end of the command list.\n");
76 log(" flatten design before synthesis\n");
79 log(" run 'abc' with -dff option\n");
82 log("The following commands are executed by this synthesis command:\n");
87 std::string top_opt
, edif_file
, blif_file
, arch
;
88 bool flatten
, retime
, vpr
, nobram
, nodram
, nosrl
;
90 void clear_flags() YS_OVERRIDE
92 top_opt
= "-auto-top";
104 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
106 std::string run_from
, run_to
;
110 for (argidx
= 1; argidx
< args
.size(); argidx
++)
112 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
113 top_opt
= "-top " + args
[++argidx
];
116 if (args
[argidx
] == "-arch" && argidx
+1 < args
.size()) {
117 arch
= args
[++argidx
];
120 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
121 edif_file
= args
[++argidx
];
124 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
125 blif_file
= args
[++argidx
];
128 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
129 size_t pos
= args
[argidx
+1].find(':');
130 if (pos
== std::string::npos
)
132 run_from
= args
[++argidx
].substr(0, pos
);
133 run_to
= args
[argidx
].substr(pos
+1);
136 if (args
[argidx
] == "-flatten") {
140 if (args
[argidx
] == "-retime") {
144 if (args
[argidx
] == "-vpr") {
148 if (args
[argidx
] == "-nobram") {
152 if (args
[argidx
] == "-nodram") {
156 if (args
[argidx
] == "-nosrl") {
162 extra_args(args
, argidx
, design
);
164 if (arch
!= "xcup" && arch
!= "xcu" && arch
!= "xc7" && arch
!= "xc6s")
165 log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch
.c_str());
167 if (!design
->full_selection())
168 log_cmd_error("This command only operates on fully selected designs!\n");
170 log_header(design
, "Executing SYNTH_XILINX pass.\n");
173 run_script(design
, run_from
, run_to
);
178 void script() YS_OVERRIDE
180 if (check_label("begin")) {
182 run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
184 run("read_verilog -lib +/xilinx/cells_sim.v");
186 run("read_verilog -lib +/xilinx/cells_xtra.v");
188 if (!nobram
|| help_mode
)
189 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
191 run(stringf("hierarchy -check %s", top_opt
.c_str()));
194 if (check_label("flatten", "(with '-flatten' only)")) {
195 if (flatten
|| help_mode
) {
201 if (check_label("coarse")) {
202 run("synth -run coarse");
205 if (check_label("bram", "(skip if '-nobram')")) {
206 if (!nobram
|| help_mode
) {
207 run("memory_bram -rules +/xilinx/brams.txt");
208 run("techmap -map +/xilinx/brams_map.v");
212 if (check_label("dram", "(skip if '-nodram')")) {
213 if (!nodram
|| help_mode
) {
214 run("memory_bram -rules +/xilinx/drams.txt");
215 run("techmap -map +/xilinx/drams_map.v");
219 if (check_label("fine")) {
220 // shregmap -tech xilinx can cope with $shiftx and $mux
221 // cells for identifiying variable-length shift registers,
222 // so attempt to convert $pmux-es to the former
223 if (!nosrl
|| help_mode
)
224 run("pmux2shiftx", "(skip if '-nosrl')");
226 run("opt -fast -full");
232 if (!vpr
|| help_mode
)
233 run("techmap -map +/xilinx/arith_map.v");
235 run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
237 if (!nosrl
|| help_mode
) {
238 // shregmap operates on bit-level flops, not word-level,
239 // so break those down here
240 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
241 // shregmap with '-tech xilinx' infers variable length shift regs
242 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
249 if (check_label("map_cells")) {
250 run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
254 if (check_label("map_luts")) {
256 run("abc -luts 2:2,3,6:5,10,20 [-dff]");
258 run("abc -luts 2:2,3,6:5,10,20" + string(retime
? " -dff" : ""));
260 // This shregmap call infers fixed length shift registers after abc
261 // has performed any necessary retiming
262 if (!nosrl
|| help_mode
)
263 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
264 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
265 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
266 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
270 if (check_label("check")) {
271 run("hierarchy -check");
273 run("check -noinit");
276 if (check_label("edif")) {
277 if (!edif_file
.empty() || help_mode
)
278 run(stringf("write_edif -pvector bra %s", edif_file
.c_str()));
281 if (check_label("blif")) {
282 if (!blif_file
.empty() || help_mode
)
283 run(stringf("write_blif %s", edif_file
.c_str()));
288 PRIVATE_NAMESPACE_END