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Revert drop down to 24x16 multipliers for all
[yosys.git] / techlibs / xilinx / synth_xilinx.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 #define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
30 // to one LUT6 (instead of a LUT5 + LUT2)
31
32 struct SynthXilinxPass : public ScriptPass
33 {
34 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
35
36 void help() YS_OVERRIDE
37 {
38 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
39 log("\n");
40 log(" synth_xilinx [options]\n");
41 log("\n");
42 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
43 log("partly selected designs. At the moment this command creates netlists that are\n");
44 log("compatible with 7-Series Xilinx devices.\n");
45 log("\n");
46 log(" -top <module>\n");
47 log(" use the specified module as top module\n");
48 log("\n");
49 log(" -family {xcup|xcu|xc7|xc6s}\n");
50 log(" run synthesis for the specified Xilinx architecture\n");
51 log(" generate the synthesis netlist for the specified family.\n");
52 log(" default: xc7\n");
53 log("\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
57 log("\n");
58 log(" -blif <file>\n");
59 log(" write the design to the specified BLIF file. writing of an output file\n");
60 log(" is omitted if this parameter is not specified.\n");
61 log("\n");
62 log(" -vpr\n");
63 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
64 log(" (this feature is experimental and incomplete)\n");
65 log("\n");
66 log(" -nobram\n");
67 log(" disable inference of block rams\n");
68 log("\n");
69 log(" -nodram\n");
70 log(" disable inference of distributed rams\n");
71 log("\n");
72 log(" -nosrl\n");
73 log(" disable inference of shift registers\n");
74 log("\n");
75 log(" -nocarry\n");
76 log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
77 log("\n");
78 log(" -nowidelut\n");
79 log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
80 log("\n");
81 log(" -nodsp\n");
82 log(" do not use DSP48E1s to implement multipliers and associated logic\n");
83 log("\n");
84 log(" -widemux <int>\n");
85 log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
86 log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
87 log(" default: 0 (no inference)\n");
88 log("\n");
89 log(" -run <from_label>:<to_label>\n");
90 log(" only run the commands between the labels (see below). an empty\n");
91 log(" from label is synonymous to 'begin', and empty to label is\n");
92 log(" synonymous to the end of the command list.\n");
93 log("\n");
94 log(" -flatten\n");
95 log(" flatten design before synthesis\n");
96 log("\n");
97 log(" -retime\n");
98 log(" run 'abc' with -dff option\n");
99 log("\n");
100 log(" -abc9\n");
101 log(" use new ABC9 flow (EXPERIMENTAL)\n");
102 log("\n");
103 log("\n");
104 log("The following commands are executed by this synthesis command:\n");
105 help_script();
106 log("\n");
107 }
108
109 std::string top_opt, edif_file, blif_file, family;
110 bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, nodsp, abc9;
111 int widemux;
112
113 void clear_flags() YS_OVERRIDE
114 {
115 top_opt = "-auto-top";
116 edif_file.clear();
117 blif_file.clear();
118 family = "xc7";
119 flatten = false;
120 retime = false;
121 vpr = false;
122 nocarry = false;
123 nobram = false;
124 nodram = false;
125 nosrl = false;
126 nocarry = false;
127 nowidelut = false;
128 nodsp = false;
129 abc9 = false;
130 widemux = 0;
131 }
132
133 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
134 {
135 std::string run_from, run_to;
136 clear_flags();
137
138 size_t argidx;
139 for (argidx = 1; argidx < args.size(); argidx++)
140 {
141 if (args[argidx] == "-top" && argidx+1 < args.size()) {
142 top_opt = "-top " + args[++argidx];
143 continue;
144 }
145 if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
146 family = args[++argidx];
147 continue;
148 }
149 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
150 edif_file = args[++argidx];
151 continue;
152 }
153 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
154 blif_file = args[++argidx];
155 continue;
156 }
157 if (args[argidx] == "-run" && argidx+1 < args.size()) {
158 size_t pos = args[argidx+1].find(':');
159 if (pos == std::string::npos)
160 break;
161 run_from = args[++argidx].substr(0, pos);
162 run_to = args[argidx].substr(pos+1);
163 continue;
164 }
165 if (args[argidx] == "-flatten") {
166 flatten = true;
167 continue;
168 }
169 if (args[argidx] == "-retime") {
170 retime = true;
171 continue;
172 }
173 if (args[argidx] == "-nocarry") {
174 nocarry = true;
175 continue;
176 }
177 if (args[argidx] == "-nowidelut") {
178 nowidelut = true;
179 continue;
180 }
181 if (args[argidx] == "-vpr") {
182 vpr = true;
183 continue;
184 }
185 if (args[argidx] == "-nocarry") {
186 nocarry = true;
187 continue;
188 }
189 if (args[argidx] == "-nobram") {
190 nobram = true;
191 continue;
192 }
193 if (args[argidx] == "-nodram") {
194 nodram = true;
195 continue;
196 }
197 if (args[argidx] == "-nosrl") {
198 nosrl = true;
199 continue;
200 }
201 if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
202 widemux = std::stoi(args[++argidx]);
203 continue;
204 }
205 if (args[argidx] == "-abc9") {
206 abc9 = true;
207 continue;
208 }
209 if (args[argidx] == "-nodsp") {
210 nodsp = true;
211 continue;
212 }
213 break;
214 }
215 extra_args(args, argidx, design);
216
217 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
218 log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
219
220 if (widemux != 0 && widemux < 2)
221 log_cmd_error("-widemux value must be 0 or >= 2.\n");
222
223 if (!design->full_selection())
224 log_cmd_error("This command only operates on fully selected designs!\n");
225
226 if (abc9 && retime)
227 log_cmd_error("-retime option not currently compatible with -abc9!\n");
228
229 log_header(design, "Executing SYNTH_XILINX pass.\n");
230 log_push();
231
232 run_script(design, run_from, run_to);
233
234 log_pop();
235 }
236
237 void script() YS_OVERRIDE
238 {
239 if (check_label("begin")) {
240 if (vpr)
241 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
242 else
243 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
244
245 run("read_verilog -lib +/xilinx/cells_xtra.v");
246
247 if (help_mode) {
248 run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
249 } else if (family == "xc6s") {
250 run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
251 } else if (family == "xc7") {
252 run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
253 }
254
255 run(stringf("hierarchy -check %s", top_opt.c_str()));
256 }
257
258 if (check_label("coarse")) {
259 run("proc");
260 if (flatten || help_mode)
261 run("flatten", "(with '-flatten')");
262 run("opt_expr");
263 run("opt_clean");
264 run("check");
265 run("opt");
266 if (help_mode)
267 run("wreduce [-keepdc]", "(option for '-widemux')");
268 else
269 run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
270 run("peepopt");
271 run("opt_clean");
272
273 if (widemux > 0 || help_mode)
274 run("muxpack", " ('-widemux' only)");
275
276 // shregmap -tech xilinx can cope with $shiftx and $mux
277 // cells for identifying variable-length shift registers,
278 // so attempt to convert $pmux-es to the former
279 // Also: wide multiplexer inference benefits from this too
280 if (!(nosrl && widemux == 0) || help_mode) {
281 run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
282 run("clean", " (skip if '-nosrl' and '-widemux=0')");
283 }
284
285 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
286
287 // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
288 // Due to current limitations of mul2dsp, we are actually mapping as a 24x17
289 // unsigned multiply with MSBs set to 1'b0
290
291 if (!nodsp || help_mode)
292 run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
293
294 run("alumacc");
295 run("share");
296 run("opt");
297 run("fsm");
298 run("opt -fast");
299 run("memory -nomap");
300 run("opt_clean");
301 }
302
303 if (check_label("bram", "(skip if '-nobram')")) {
304 if (help_mode) {
305 run("memory_bram -rules +/xilinx/{family}_brams.txt");
306 run("techmap -map +/xilinx/{family}_brams_map.v");
307 } else if (!nobram) {
308 if (family == "xc6s") {
309 run("memory_bram -rules +/xilinx/xc6s_brams.txt");
310 run("techmap -map +/xilinx/xc6s_brams_map.v");
311 } else if (family == "xc7") {
312 run("memory_bram -rules +/xilinx/xc7_brams.txt");
313 run("techmap -map +/xilinx/xc7_brams_map.v");
314 } else {
315 log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
316 }
317 }
318 }
319
320 if (check_label("dram", "(skip if '-nodram')")) {
321 if (!nodram || help_mode) {
322 run("memory_bram -rules +/xilinx/drams.txt");
323 run("techmap -map +/xilinx/drams_map.v");
324 }
325 }
326
327 if (check_label("fine")) {
328 if (widemux > 0)
329 run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
330 // performs less efficiently
331 else
332 run("opt -fast -full");
333 run("memory_map");
334 run("dffsr2dff");
335 run("dff2dffe");
336 if (help_mode || !nodsp) {
337 run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')");
338 run("xilinx_dsp", " (skip if '-nodsp')");
339 }
340 if (help_mode) {
341 run("simplemap t:$mux", " ('-widemux' only)");
342 run("muxcover <internal options>, ('-widemux' only)");
343 }
344 else if (widemux > 0) {
345 run("simplemap t:$mux");
346 constexpr int cost_mux2 = 100;
347 std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
348 switch (widemux) {
349 case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
350 case 3:
351 case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
352 case 5:
353 case 6:
354 case 7:
355 case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
356 case 9:
357 case 10:
358 case 11:
359 case 12:
360 case 13:
361 case 14:
362 case 15:
363 default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
364 }
365 run("muxcover " + muxcover_args);
366 }
367 run("opt -full");
368
369 if (!nosrl || help_mode) {
370 // shregmap operates on bit-level flops, not word-level,
371 // so break those down here
372 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
373 // shregmap with '-tech xilinx' infers variable length shift regs
374 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
375 }
376
377 std::string techmap_args = " -map +/techmap.v";
378 if (help_mode)
379 techmap_args += " [-map +/xilinx/mux_map.v]";
380 else if (widemux > 0)
381 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
382 if (help_mode)
383 techmap_args += " [-map +/xilinx/arith_map.v]";
384 else if (!nocarry) {
385 techmap_args += " -map +/xilinx/arith_map.v";
386 if (vpr)
387 techmap_args += " -D _EXPLICIT_CARRY";
388 else if (abc9)
389 techmap_args += " -D _CLB_CARRY";
390 }
391 run("techmap " + techmap_args);
392 run("opt -fast");
393 }
394
395 if (check_label("map_cells")) {
396 std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
397 if (widemux > 0)
398 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
399 run("techmap " + techmap_args);
400 run("clean");
401 }
402
403 if (check_label("map_luts")) {
404 run("opt_expr -mux_undef");
405 if (help_mode)
406 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
407 else if (abc9) {
408 if (family != "xc7")
409 log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
410 if (nowidelut)
411 run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
412 else
413 run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
414 }
415 else {
416 if (nowidelut)
417 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
418 else
419 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
420 }
421 run("clean");
422
423 // This shregmap call infers fixed length shift registers after abc
424 // has performed any necessary retiming
425 if (!nosrl || help_mode)
426 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
427 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
428 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
429 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
430 run("clean");
431 }
432
433 if (check_label("check")) {
434 run("hierarchy -check");
435 run("stat -tech xilinx");
436 run("check -noinit");
437 }
438
439 if (check_label("edif")) {
440 if (!edif_file.empty() || help_mode)
441 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
442 }
443
444 if (check_label("blif")) {
445 if (!blif_file.empty() || help_mode)
446 run(stringf("write_blif %s", edif_file.c_str()));
447 }
448 }
449 } SynthXilinxPass;
450
451 PRIVATE_NAMESPACE_END