techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
  29                              // to one LUT6 (instead of a LUT5 + LUT2)
  30
  31 struct SynthXilinxPass : public ScriptPass
  32 {
  33         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  34
  35         void help() YS_OVERRIDE
  36         {
  37                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  38                 log("\n");
  39                 log("    synth_xilinx [options]\n");
  40                 log("\n");
  41                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  42                 log("partly selected designs. At the moment this command creates netlists that are\n");
  43                 log("compatible with 7-Series Xilinx devices.\n");
  44                 log("\n");
  45                 log("    -top <module>\n");
  46                 log("        use the specified module as top module\n");
  47                 log("\n");
  48                 log("    -family {xcup|xcu|xc7|xc6s}\n");
  49                 log("        run synthesis for the specified Xilinx architecture\n");
  50                 log("        generate the synthesis netlist for the specified family.\n");
  51                 log("        default: xc7\n");
  52                 log("\n");
  53                 log("    -edif <file>\n");
  54                 log("        write the design to the specified edif file. writing of an output file\n");
  55                 log("        is omitted if this parameter is not specified.\n");
  56                 log("\n");
  57                 log("    -blif <file>\n");
  58                 log("        write the design to the specified BLIF file. writing of an output file\n");
  59                 log("        is omitted if this parameter is not specified.\n");
  60                 log("\n");
  61                 log("    -vpr\n");
  62                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  63                 log("        (this feature is experimental and incomplete)\n");
  64                 log("\n");
  65                 log("    -nobram\n");
  66                 log("        disable inference of block rams\n");
  67                 log("\n");
  68                 log("    -nodram\n");
  69                 log("        disable inference of distributed rams\n");
  70                 log("\n");
  71                 log("    -nosrl\n");
  72                 log("        disable inference of shift registers\n");
  73                 log("\n");
  74                 log("    -nocarry\n");
  75                 log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
  76                 log("\n");
  77                 log("    -nowidelut\n");
  78                 log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
  79                 log("\n");
  80                 log("    -widemux <int>\n");
  81                 log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
  82                 log("        above this number of inputs (minimum value 5).\n");
  83                 log("        default: 0 (no inference)\n");
  84                 log("\n");
  85                 log("    -run <from_label>:<to_label>\n");
  86                 log("        only run the commands between the labels (see below). an empty\n");
  87                 log("        from label is synonymous to 'begin', and empty to label is\n");
  88                 log("        synonymous to the end of the command list.\n");
  89                 log("\n");
  90                 log("    -flatten\n");
  91                 log("        flatten design before synthesis\n");
  92                 log("\n");
  93                 log("    -retime\n");
  94                 log("        run 'abc' with -dff option\n");
  95                 log("\n");
  96                 log("    -abc9\n");
  97                 log("        use new ABC9 flow (EXPERIMENTAL)\n");
  98                 log("\n");
  99                 log("\n");
 100                 log("The following commands are executed by this synthesis command:\n");
 101                 help_script();
 102                 log("\n");
 103         }
 104
 105         std::string top_opt, edif_file, blif_file, family;
 106         bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 107         int widemux;
 108
 109         void clear_flags() YS_OVERRIDE
 110         {
 111                 top_opt = "-auto-top";
 112                 edif_file.clear();
 113                 blif_file.clear();
 114                 family = "xc7";
 115                 flatten = false;
 116                 retime = false;
 117                 vpr = false;
 118                 nocarry = false;
 119                 nobram = false;
 120                 nodram = false;
 121                 nosrl = false;
 122                 nocarry = false;
 123                 nowidelut = false;
 124                 abc9 = false;
 125                 widemux = 0;
 126         }
 127
 128         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 129         {
 130                 std::string run_from, run_to;
 131                 clear_flags();
 132
 133                 size_t argidx;
 134                 for (argidx = 1; argidx < args.size(); argidx++)
 135                 {
 136                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 137                                 top_opt = "-top " + args[++argidx];
 138                                 continue;
 139                         }
 140                         if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
 141                                 family = args[++argidx];
 142                                 continue;
 143                         }
 144                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 145                                 edif_file = args[++argidx];
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 149                                 blif_file = args[++argidx];
 150                                 continue;
 151                         }
 152                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 153                                 size_t pos = args[argidx+1].find(':');
 154                                 if (pos == std::string::npos)
 155                                         break;
 156                                 run_from = args[++argidx].substr(0, pos);
 157                                 run_to = args[argidx].substr(pos+1);
 158                                 continue;
 159                         }
 160                         if (args[argidx] == "-flatten") {
 161                                 flatten = true;
 162                                 continue;
 163                         }
 164                         if (args[argidx] == "-retime") {
 165                                 retime = true;
 166                                 continue;
 167                         }
 168                         if (args[argidx] == "-nocarry") {
 169                                 nocarry = true;
 170                                 continue;
 171                         }
 172                         if (args[argidx] == "-nowidelut") {
 173                                 nowidelut = true;
 174                                 continue;
 175                         }
 176                         if (args[argidx] == "-vpr") {
 177                                 vpr = true;
 178                                 continue;
 179                         }
 180                         if (args[argidx] == "-nocarry") {
 181                                 nocarry = true;
 182                                 continue;
 183                         }
 184                         if (args[argidx] == "-nobram") {
 185                                 nobram = true;
 186                                 continue;
 187                         }
 188                         if (args[argidx] == "-nodram") {
 189                                 nodram = true;
 190                                 continue;
 191                         }
 192                         if (args[argidx] == "-nosrl") {
 193                                 nosrl = true;
 194                                 continue;
 195                         }
 196                         if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
 197                                 widemux = atoi(args[++argidx].c_str());
 198                                 continue;
 199                         }
 200                         if (args[argidx] == "-abc9") {
 201                                 abc9 = true;
 202                                 continue;
 203                         }
 204                         break;
 205                 }
 206                 extra_args(args, argidx, design);
 207
 208                 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
 209                         log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
 210
 211                 if (widemux != 0 && widemux < 5)
 212                         log_cmd_error("-widemux value must be 0 or >= 5.\n");
 213
 214                 if (!design->full_selection())
 215                         log_cmd_error("This command only operates on fully selected designs!\n");
 216
 217                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 218                 log_push();
 219
 220                 run_script(design, run_from, run_to);
 221
 222                 log_pop();
 223         }
 224
 225         void script() YS_OVERRIDE
 226         {
 227                 if (check_label("begin")) {
 228                         if (vpr)
 229                                 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 230                         else
 231                                 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
 232
 233                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 234
 235                         if (!nobram || help_mode)
 236                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 237
 238                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 239                 }
 240
 241                 if (check_label("coarse")) {
 242                         if (help_mode)
 243                                 run("synth -run coarse [-flatten]", "(with '-flatten')");
 244                         else
 245                                 run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
 246
 247                         if (widemux > 0 || help_mode)
 248                                 run("muxpack", "    ('-widemux' only)");
 249
 250                         // shregmap -tech xilinx can cope with $shiftx and $mux
 251                         //   cells for identifying variable-length shift registers,
 252                         //   so attempt to convert $pmux-es to the former
 253                         // Also: wide multiplexer inference benefits from this too
 254                         if (!(nosrl && widemux == 0) || help_mode)
 255                                 run("pmux2shiftx", "(skip if '-nosrl' and '-widemux' < 5)");
 256                 }
 257
 258                 if (check_label("bram", "(skip if '-nobram')")) {
 259                         if (!nobram || help_mode) {
 260                                 run("memory_bram -rules +/xilinx/brams.txt");
 261                                 run("techmap -map +/xilinx/brams_map.v");
 262                         }
 263                 }
 264
 265                 if (check_label("dram", "(skip if '-nodram')")) {
 266                         if (!nodram || help_mode) {
 267                                 run("memory_bram -rules +/xilinx/drams.txt");
 268                                 run("techmap -map +/xilinx/drams_map.v");
 269                         }
 270                 }
 271
 272                 if (check_label("fine")) {
 273                         run("opt -fast -full");
 274                         run("memory_map");
 275                         run("dffsr2dff");
 276                         run("dff2dffe");
 277                         if (help_mode) {
 278                                 run("simplemap t:$mux", "         ('-widemux' only)");
 279                                 run("muxcover <internal options>, ('-widemux' only)");
 280                         }
 281                         else if (widemux > 0) {
 282                                 run("simplemap t:$mux");
 283                                 std::string muxcover_args = " -nodecode";
 284                                 switch (widemux) {
 285                                         // NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
 286                                         //     of those so that 4:1 muxes and below are implemented
 287                                         //     out of mux2s
 288                                         case  5: muxcover_args += " -mux8=350 -mux16=400"; break;
 289                                         case  6: muxcover_args += " -mux8=450 -mux16=500"; break;
 290                                         case  7: muxcover_args += " -mux8=550 -mux16=600"; break;
 291                                         case  8: muxcover_args += " -mux8=650 -mux16=700"; break;
 292                                         case  9: muxcover_args += " -mux16=750"; break;
 293                                         case 10: muxcover_args += " -mux16=850"; break;
 294                                         case 11: muxcover_args += " -mux16=950"; break;
 295                                         case 12: muxcover_args += " -mux16=1050"; break;
 296                                         case 13: muxcover_args += " -mux16=1150"; break;
 297                                         case 14: muxcover_args += " -mux16=1250"; break;
 298                                         case 15: muxcover_args += " -mux16=1350"; break;
 299                                         default: muxcover_args += " -mux16=1450"; break;
 300                                 }
 301                                 run("muxcover " + muxcover_args);
 302                         }
 303                         run("opt -full");
 304
 305                         if (!nosrl || help_mode) {
 306                                 // shregmap operates on bit-level flops, not word-level,
 307                                 //   so break those down here
 308                                 run("simplemap t:$dff t:$dffe", "       (skip if '-nosrl')");
 309                                 // shregmap with '-tech xilinx' infers variable length shift regs
 310                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 311                         }
 312
 313                         std::string techmap_args = " -map +/techmap.v";
 314                         if (help_mode)
 315                                 techmap_args += " [-map +/xilinx/mux_map.v]";
 316                         else if (widemux > 0)
 317                                 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
 318                         if (help_mode)
 319                                 techmap_args += " [-map +/xilinx/arith_map.v]";
 320                         else if (!nocarry) {
 321                                 techmap_args += " -map +/xilinx/arith_map.v";
 322                                 if (vpr)
 323                                         techmap_args += " -D _EXPLICIT_CARRY";
 324                                 else if (abc9)
 325                                         techmap_args += " -D _CLB_CARRY";
 326                         }
 327                         run("techmap " + techmap_args);
 328                         run("opt -fast");
 329                 }
 330
 331                 if (check_label("map_cells")) {
 332                         std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
 333                         if (widemux > 0)
 334                                 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 335                         run("techmap " + techmap_args);
 336                         run("clean");
 337                 }
 338
 339                 if (check_label("map_luts")) {
 340                         run("opt_expr -mux_undef");
 341                         if (help_mode)
 342                                 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
 343                         else if (abc9) {
 344                                 if (family != "xc7")
 345                                         log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 346                                 if (nowidelut)
 347                                         run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 348                                 else
 349                                         run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 350                         }
 351                         else {
 352                                 if (nowidelut)
 353                                         run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 354                                 else
 355                                         run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 356                         }
 357                         run("clean");
 358
 359                         // This shregmap call infers fixed length shift registers after abc
 360                         //   has performed any necessary retiming
 361                         if (!nosrl || help_mode)
 362                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 363                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 364                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 365                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 366                         run("clean");
 367                 }
 368
 369                 if (check_label("check")) {
 370                         run("hierarchy -check");
 371                         run("stat -tech xilinx");
 372                         run("check -noinit");
 373                 }
 374
 375                 if (check_label("edif")) {
 376                         if (!edif_file.empty() || help_mode)
 377                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 378                 }
 379
 380                 if (check_label("blif")) {
 381                         if (!blif_file.empty() || help_mode)
 382                                 run(stringf("write_blif %s", edif_file.c_str()));
 383                 }
 384         }
 385 } SynthXilinxPass;
 386
 387 PRIVATE_NAMESPACE_END