2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
29 // to one LUT6 (instead of a LUT5 + LUT2)
31 struct SynthXilinxPass
: public ScriptPass
33 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
35 void help() YS_OVERRIDE
37 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
39 log(" synth_xilinx [options]\n");
41 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
42 log("partly selected designs. At the moment this command creates netlists that are\n");
43 log("compatible with 7-Series Xilinx devices.\n");
45 log(" -top <module>\n");
46 log(" use the specified module as top module\n");
48 log(" -arch {xcup|xcu|xc7|xc6s}\n");
49 log(" run synthesis for the specified Xilinx architecture\n");
50 log(" default: xc7\n");
52 log(" -edif <file>\n");
53 log(" write the design to the specified edif file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
56 log(" -blif <file>\n");
57 log(" write the design to the specified BLIF file. writing of an output file\n");
58 log(" is omitted if this parameter is not specified.\n");
61 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
62 log(" (this feature is experimental and incomplete)\n");
65 log(" disable inference of carry chains\n");
68 log(" disable inference of block rams\n");
71 log(" disable inference of distributed rams\n");
74 log(" disable inference of shift registers\n");
76 log(" -minmuxf <int>\n");
77 log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
78 log(" above this number of inputs (minimum value 5).\n");
79 log(" default: 0 (no inference)\n");
81 log(" -run <from_label>:<to_label>\n");
82 log(" only run the commands between the labels (see below). an empty\n");
83 log(" from label is synonymous to 'begin', and empty to label is\n");
84 log(" synonymous to the end of the command list.\n");
87 log(" flatten design before synthesis\n");
90 log(" run 'abc' with -dff option\n");
93 log(" use new ABC9 flow (EXPERIMENTAL)\n");
96 log("The following commands are executed by this synthesis command:\n");
101 std::string top_opt
, edif_file
, blif_file
, abc
, arch
;
102 bool flatten
, retime
, vpr
, nocarry
, nobram
, nodram
, nosrl
;
105 void clear_flags() YS_OVERRIDE
107 top_opt
= "-auto-top";
122 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
124 std::string run_from
, run_to
;
128 for (argidx
= 1; argidx
< args
.size(); argidx
++)
130 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
131 top_opt
= "-top " + args
[++argidx
];
134 if (args
[argidx
] == "-arch" && argidx
+1 < args
.size()) {
135 arch
= args
[++argidx
];
138 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
139 edif_file
= args
[++argidx
];
142 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
143 blif_file
= args
[++argidx
];
146 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
147 size_t pos
= args
[argidx
+1].find(':');
148 if (pos
== std::string::npos
)
150 run_from
= args
[++argidx
].substr(0, pos
);
151 run_to
= args
[argidx
].substr(pos
+1);
154 if (args
[argidx
] == "-flatten") {
158 if (args
[argidx
] == "-retime") {
162 if (args
[argidx
] == "-vpr") {
166 if (args
[argidx
] == "-nocarry") {
170 if (args
[argidx
] == "-nobram") {
174 if (args
[argidx
] == "-nodram") {
178 if (args
[argidx
] == "-nosrl") {
182 if (args
[argidx
] == "-minmuxf" && argidx
+1 < args
.size()) {
183 minmuxf
= atoi(args
[++argidx
].c_str());
186 if (args
[argidx
] == "-abc9") {
192 extra_args(args
, argidx
, design
);
194 if (arch
!= "xcup" && arch
!= "xcu" && arch
!= "xc7" && arch
!= "xc6s")
195 log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch
.c_str());
197 if (minmuxf
!= 0 && minmuxf
< 5)
198 log_cmd_error("-minmuxf value must be 0 or >= 5.\n");
200 if (!design
->full_selection())
201 log_cmd_error("This command only operates on fully selected designs!\n");
203 log_header(design
, "Executing SYNTH_XILINX pass.\n");
206 run_script(design
, run_from
, run_to
);
211 void script() YS_OVERRIDE
213 if (check_label("begin")) {
215 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
217 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
219 run("read_verilog -lib +/xilinx/cells_xtra.v");
221 if (!nobram
|| help_mode
)
222 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
224 run(stringf("hierarchy -check %s", top_opt
.c_str()));
227 if (check_label("coarse")) {
229 if (flatten
|| help_mode
)
230 run("flatten", "(with -flatten only)");
236 run("wreduce [c:* t:$mux %d]", "(selection for '-minmuxf' only)");
238 run("wreduce" + std::string(minmuxf
> 0 ? " c:* t:$mux %d" : ""));
246 run("memory -nomap");
249 if (minmuxf
> 0 || help_mode
)
250 run("muxpack", " ('-minmuxf' only)");
252 // shregmap -tech xilinx can cope with $shiftx and $mux
253 // cells for identifying variable-length shift registers,
254 // so attempt to convert $pmux-es to the former
255 // Also: wide multiplexer inference benefits from this too
256 if (!(nosrl
&& minmuxf
== 0) || help_mode
)
257 run("pmux2shiftx", "(skip if '-nosrl' and '-minmuxf' < 5)");
260 if (check_label("bram", "(skip if '-nobram')")) {
261 if (!nobram
|| help_mode
) {
262 run("memory_bram -rules +/xilinx/brams.txt");
263 run("techmap -map +/xilinx/brams_map.v");
267 if (check_label("dram", "(skip if '-nodram')")) {
268 if (!nodram
|| help_mode
) {
269 run("memory_bram -rules +/xilinx/drams.txt");
270 run("techmap -map +/xilinx/drams_map.v");
274 if (check_label("fine")) {
279 if (minmuxf
> 0 || help_mode
) {
280 run("simplemap t:$mux", " ('-minmuxf' only)");
281 if (minmuxf
> 0 || help_mode
) {
282 std::string muxcover_args
= " -dmux=0";
284 // NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
285 // of those so that 4:1 muxes and below are implemented
287 case 5: muxcover_args
+= " -mux8=350 -mux16=400"; break;
288 case 6: muxcover_args
+= " -mux8=450 -mux16=500"; break;
289 case 7: muxcover_args
+= " -mux8=550 -mux16=600"; break;
290 case 8: muxcover_args
+= " -mux8=650 -mux16=700"; break;
291 case 9: muxcover_args
+= " -mux16=750"; break;
292 case 10: muxcover_args
+= " -mux16=850"; break;
293 case 11: muxcover_args
+= " -mux16=950"; break;
294 case 12: muxcover_args
+= " -mux16=1050"; break;
295 case 13: muxcover_args
+= " -mux16=1150"; break;
296 case 14: muxcover_args
+= " -mux16=1250"; break;
297 case 15: muxcover_args
+= " -mux16=1350"; break;
298 default: muxcover_args
+= " -mux16=1450"; break;
300 run("muxcover " + muxcover_args
, "('-minmuxf' only)");
305 if (!nosrl
|| help_mode
) {
306 // shregmap operates on bit-level flops, not word-level,
307 // so break those down here
308 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
309 // shregmap with '-tech xilinx' infers variable length shift regs
310 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
313 std::string techmap_args
= " -map +/techmap.v";
315 techmap_args
+= " [-map +/xilinx/mux_map.v]";
316 else if (minmuxf
> 0)
317 techmap_args
+= stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", minmuxf
);
319 techmap_args
+= " [-map +/xilinx/arith_map.v]";
321 techmap_args
+= " -map +/xilinx/arith_map.v";
323 techmap_args
+= " -D _EXPLICIT_CARRY";
324 else if (abc
== "abc9")
325 techmap_args
+= " -D _CLB_CARRY";
327 run("techmap " + techmap_args
);
331 if (check_label("map_cells")) {
332 std::string techmap_args
= "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
334 techmap_args
+= stringf(" -D MIN_MUX_INPUTS=%d", minmuxf
);
335 run("techmap " + techmap_args
);
339 if (check_label("map_luts")) {
340 run("opt_expr -mux_undef");
342 run(abc
+ " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY
+ string(retime
? " -dff" : ""));
344 run(abc
+ " -luts 2:2,3,6:5,10,20 [-dff]");
346 run(abc
+ " -luts 2:2,3,6:5,10,20" + string(retime
? " -dff" : ""));
349 // This shregmap call infers fixed length shift registers after abc
350 // has performed any necessary retiming
351 if (!nosrl
|| help_mode
)
352 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
353 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
354 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
355 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
359 if (check_label("check")) {
360 run("hierarchy -check");
361 run("stat -tech xilinx");
362 run("check -noinit");
365 if (check_label("edif")) {
366 if (!edif_file
.empty() || help_mode
)
367 run(stringf("write_edif -pvector bra %s", edif_file
.c_str()));
370 if (check_label("blif")) {
371 if (!blif_file
.empty() || help_mode
)
372 run(stringf("write_blif %s", edif_file
.c_str()));
377 PRIVATE_NAMESPACE_END