2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
30 if (label
== run_from
)
37 struct SynthXilinxPass
: public Pass
39 SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
41 void help() YS_OVERRIDE
43 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
45 log(" synth_xilinx [options]\n");
47 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
48 log("partly selected designs. At the moment this command creates netlists that are\n");
49 log("compatible with 7-Series Xilinx devices.\n");
51 log(" -top <module>\n");
52 log(" use the specified module as top module\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
58 log(" -blif <file>\n");
59 log(" write the design to the specified BLIF file. writing of an output file\n");
60 log(" is omitted if this parameter is not specified.\n");
63 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
64 log(" (this feature is experimental and incomplete)\n");
67 log(" disable infering of block rams\n");
70 log(" disable infering of distributed rams\n");
72 log(" -run <from_label>:<to_label>\n");
73 log(" only run the commands between the labels (see below). an empty\n");
74 log(" from label is synonymous to 'begin', and empty to label is\n");
75 log(" synonymous to the end of the command list.\n");
78 log(" flatten design before synthesis\n");
81 log(" run 'abc' with -dff option\n");
84 log("The following commands are executed by this synthesis command:\n");
87 log(" read_verilog -lib +/xilinx/cells_sim.v\n");
88 log(" read_verilog -lib +/xilinx/cells_xtra.v\n");
89 log(" read_verilog -lib +/xilinx/brams_bb.v\n");
90 log(" hierarchy -check -top <top>\n");
92 log(" flatten: (only if -flatten)\n");
97 log(" synth -run coarse\n");
99 log(" bram: (only executed when '-nobram' is not given)\n");
100 log(" memory_bram -rules +/xilinx/brams.txt\n");
101 log(" techmap -map +/xilinx/brams_map.v\n");
103 log(" dram: (only executed when '-nodram' is not given)\n");
104 log(" memory_bram -rules +/xilinx/drams.txt\n");
105 log(" techmap -map +/xilinx/drams_map.v\n");
108 log(" opt -fast -full\n");
109 log(" memory_map\n");
113 log(" simplemap t:$dff*\n");
114 log(" shregmap -tech xilinx\n");
115 log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n");
119 log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
120 log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
123 log(" map_cells:\n");
124 log(" techmap -map +/xilinx/cells_map.v\n");
125 log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
126 log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
130 log(" hierarchy -check\n");
132 log(" check -noinit\n");
134 log(" edif: (only if -edif)\n");
135 log(" write_edif <file-name>\n");
137 log(" blif: (only if -blif)\n");
138 log(" write_blif <file-name>\n");
141 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
143 std::string top_opt
= "-auto-top";
144 std::string edif_file
;
145 std::string blif_file
;
146 std::string run_from
, run_to
;
147 bool flatten
= false;
154 for (argidx
= 1; argidx
< args
.size(); argidx
++)
156 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
157 top_opt
= "-top " + args
[++argidx
];
160 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
161 edif_file
= args
[++argidx
];
164 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
165 blif_file
= args
[++argidx
];
168 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
169 size_t pos
= args
[argidx
+1].find(':');
170 if (pos
== std::string::npos
)
172 run_from
= args
[++argidx
].substr(0, pos
);
173 run_to
= args
[argidx
].substr(pos
+1);
176 if (args
[argidx
] == "-flatten") {
180 if (args
[argidx
] == "-retime") {
184 if (args
[argidx
] == "-vpr") {
188 if (args
[argidx
] == "-nobram") {
192 if (args
[argidx
] == "-nodram") {
198 extra_args(args
, argidx
, design
);
200 if (!design
->full_selection())
201 log_cmd_error("This command only operates on fully selected designs!\n");
203 bool active
= run_from
.empty();
205 log_header(design
, "Executing SYNTH_XILINX pass.\n");
208 if (check_label(active
, run_from
, run_to
, "begin"))
211 Pass::call(design
, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
213 Pass::call(design
, "read_verilog -lib +/xilinx/cells_sim.v");
216 Pass::call(design
, "read_verilog -lib +/xilinx/cells_xtra.v");
219 Pass::call(design
, "read_verilog -lib +/xilinx/brams_bb.v");
222 Pass::call(design
, stringf("hierarchy -check %s", top_opt
.c_str()));
225 if (flatten
&& check_label(active
, run_from
, run_to
, "flatten"))
227 Pass::call(design
, "proc");
228 Pass::call(design
, "flatten");
231 if (check_label(active
, run_from
, run_to
, "coarse"))
233 Pass::call(design
, "synth -run coarse");
236 if (check_label(active
, run_from
, run_to
, "bram"))
239 Pass::call(design
, "memory_bram -rules +/xilinx/brams.txt");
240 Pass::call(design
, "techmap -map +/xilinx/brams_map.v");
244 if (check_label(active
, run_from
, run_to
, "dram"))
247 Pass::call(design
, "memory_bram -rules +/xilinx/drams.txt");
248 Pass::call(design
, "techmap -map +/xilinx/drams_map.v");
252 if (check_label(active
, run_from
, run_to
, "fine"))
254 Pass::call(design
, "opt -fast -full");
255 Pass::call(design
, "memory_map");
256 Pass::call(design
, "dffsr2dff");
257 Pass::call(design
, "dff2dffe");
258 Pass::call(design
, "opt -full");
260 Pass::call(design
, "simplemap t:$dff*");
261 Pass::call(design
, "shregmap -tech xilinx");
264 Pass::call(design
, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
266 Pass::call(design
, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
269 Pass::call(design
, "opt -fast");
272 if (check_label(active
, run_from
, run_to
, "map_luts"))
274 Pass::call(design
, "abc -luts 2:2,3,6:5,10,20" + string(retime
? " -dff" : ""));
275 Pass::call(design
, "clean");
276 Pass::call(design
, "techmap -map +/xilinx/lut_map.v");
279 if (check_label(active
, run_from
, run_to
, "map_cells"))
281 Pass::call(design
, "techmap -map +/xilinx/cells_map.v");
282 Pass::call(design
, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
283 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
284 Pass::call(design
, "clean");
287 if (check_label(active
, run_from
, run_to
, "check"))
289 Pass::call(design
, "hierarchy -check");
290 Pass::call(design
, "stat");
291 Pass::call(design
, "check -noinit");
294 if (check_label(active
, run_from
, run_to
, "edif"))
296 if (!edif_file
.empty())
297 Pass::call(design
, stringf("write_edif -pvector bra %s", edif_file
.c_str()));
299 if (check_label(active
, run_from
, run_to
, "blif"))
301 if (!blif_file
.empty())
302 Pass::call(design
, stringf("write_blif %s", edif_file
.c_str()));
309 PRIVATE_NAMESPACE_END