techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
  29 {
  30         if (label == run_from)
  31                 active = true;
  32         if (label == run_to)
  33                 active = false;
  34         return active;
  35 }
  36
  37 struct SynthXilinxPass : public Pass
  38 {
  39         SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  40
  41         virtual void help()
  42         {
  43                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  44                 log("\n");
  45                 log("    synth_xilinx [options]\n");
  46                 log("\n");
  47                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  48                 log("partly selected designs. At the moment this command creates netlists that are\n");
  49                 log("compatible with 7-Series Xilinx devices.\n");
  50                 log("\n");
  51                 log("    -top <module>\n");
  52                 log("        use the specified module as top module\n");
  53                 log("\n");
  54                 log("    -edif <file>\n");
  55                 log("        write the design to the specified edif file. writing of an output file\n");
  56                 log("        is omitted if this parameter is not specified.\n");
  57                 log("\n");
  58                 log("    -blif <file>\n");
  59                 log("        write the design to the specified BLIF file. writing of an output file\n");
  60                 log("        is omitted if this parameter is not specified.\n");
  61                 log("\n");
  62                 log("    -vpr\n");
  63                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  64                 log("        (this feature is experimental and incomplete)\n");
  65                 log("\n");
  66                 log("    -run <from_label>:<to_label>\n");
  67                 log("        only run the commands between the labels (see below). an empty\n");
  68                 log("        from label is synonymous to 'begin', and empty to label is\n");
  69                 log("        synonymous to the end of the command list.\n");
  70                 log("\n");
  71                 log("    -flatten\n");
  72                 log("        flatten design before synthesis\n");
  73                 log("\n");
  74                 log("    -retime\n");
  75                 log("        run 'abc' with -dff option\n");
  76                 log("\n");
  77                 log("\n");
  78                 log("The following commands are executed by this synthesis command:\n");
  79                 log("\n");
  80                 log("    begin:\n");
  81                 log("        read_verilog -lib +/xilinx/cells_sim.v\n");
  82                 log("        read_verilog -lib +/xilinx/cells_xtra.v\n");
  83                 log("        read_verilog -lib +/xilinx/brams_bb.v\n");
  84                 log("        hierarchy -check -top <top>\n");
  85                 log("\n");
  86                 log("    flatten:     (only if -flatten)\n");
  87                 log("        proc\n");
  88                 log("        flatten\n");
  89                 log("\n");
  90                 log("    coarse:\n");
  91                 log("        synth -run coarse\n");
  92                 log("\n");
  93                 log("    bram:\n");
  94                 log("        memory_bram -rules +/xilinx/brams.txt\n");
  95                 log("        techmap -map +/xilinx/brams_map.v\n");
  96                 log("\n");
  97                 log("    dram:\n");
  98                 log("        memory_bram -rules +/xilinx/drams.txt\n");
  99                 log("        techmap -map +/xilinx/drams_map.v\n");
 100                 log("\n");
 101                 log("    fine:\n");
 102                 log("        opt -fast -full\n");
 103                 log("        memory_map\n");
 104                 log("        dffsr2dff\n");
 105                 log("        dff2dffe\n");
 106                 log("        opt -full\n");
 107                 log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
 108                 log("        opt -fast\n");
 109                 log("\n");
 110                 log("    map_luts:\n");
 111                 log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 112                 log("        clean\n");
 113                 log("\n");
 114                 log("    map_cells:\n");
 115                 log("        techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)\n");
 116                 log("        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n");
 117                 log("        clean\n");
 118                 log("\n");
 119                 log("    check:\n");
 120                 log("        hierarchy -check\n");
 121                 log("        stat\n");
 122                 log("        check -noinit\n");
 123                 log("\n");
 124                 log("    edif:     (only if -edif)\n");
 125                 log("        write_edif <file-name>\n");
 126                 log("\n");
 127                 log("    blif:     (only if -blif)\n");
 128                 log("        write_blif <file-name>\n");
 129                 log("\n");
 130         }
 131         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 132         {
 133                 std::string top_opt = "-auto-top";
 134                 std::string edif_file;
 135                 std::string blif_file;
 136                 std::string run_from, run_to;
 137                 bool flatten = false;
 138                 bool retime = false;
 139                 bool vpr = false;
 140
 141                 size_t argidx;
 142                 for (argidx = 1; argidx < args.size(); argidx++)
 143                 {
 144                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 145                                 top_opt = "-top " + args[++argidx];
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 149                                 edif_file = args[++argidx];
 150                                 continue;
 151                         }
 152                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 153                                 blif_file = args[++argidx];
 154                                 continue;
 155                         }
 156                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 157                                 size_t pos = args[argidx+1].find(':');
 158                                 if (pos == std::string::npos)
 159                                         break;
 160                                 run_from = args[++argidx].substr(0, pos);
 161                                 run_to = args[argidx].substr(pos+1);
 162                                 continue;
 163                         }
 164                         if (args[argidx] == "-flatten") {
 165                                 flatten = true;
 166                                 continue;
 167                         }
 168                         if (args[argidx] == "-retime") {
 169                                 retime = true;
 170                                 continue;
 171                         }
 172                         if (args[argidx] == "-vpr") {
 173                                 vpr = true;
 174                                 continue;
 175                         }
 176                         break;
 177                 }
 178                 extra_args(args, argidx, design);
 179
 180                 if (!design->full_selection())
 181                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 182
 183                 bool active = run_from.empty();
 184
 185                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 186                 log_push();
 187
 188                 if (check_label(active, run_from, run_to, "begin"))
 189                 {
 190                         Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
 191                         Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 192                         Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
 193                         Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 194                 }
 195
 196                 if (flatten && check_label(active, run_from, run_to, "flatten"))
 197                 {
 198                         Pass::call(design, "proc");
 199                         Pass::call(design, "flatten");
 200                 }
 201
 202                 if (check_label(active, run_from, run_to, "coarse"))
 203                 {
 204                         Pass::call(design, "synth -run coarse");
 205                 }
 206
 207                 if (check_label(active, run_from, run_to, "bram"))
 208                 {
 209                         Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
 210                         Pass::call(design, "techmap -map +/xilinx/brams_map.v");
 211                 }
 212
 213                 if (check_label(active, run_from, run_to, "dram"))
 214                 {
 215                         Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
 216                         Pass::call(design, "techmap -map +/xilinx/drams_map.v");
 217                 }
 218
 219                 if (check_label(active, run_from, run_to, "fine"))
 220                 {
 221                         Pass::call(design, "opt -fast -full");
 222                         Pass::call(design, "memory_map");
 223                         Pass::call(design, "dffsr2dff");
 224                         Pass::call(design, "dff2dffe");
 225                         Pass::call(design, "opt -full");
 226                         Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 227                         Pass::call(design, "opt -fast");
 228                 }
 229
 230                 if (check_label(active, run_from, run_to, "map_luts"))
 231                 {
 232                         Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 233                         Pass::call(design, "clean");
 234                 }
 235
 236                 if (check_label(active, run_from, run_to, "map_cells"))
 237                 {
 238                         if (vpr)
 239                             Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v");
 240                         else
 241                             Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 242                         Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
 243                         Pass::call(design, "clean");
 244                 }
 245
 246                 if (check_label(active, run_from, run_to, "check"))
 247                 {
 248                         Pass::call(design, "hierarchy -check");
 249                         Pass::call(design, "stat");
 250                         Pass::call(design, "check -noinit");
 251                 }
 252
 253                 if (check_label(active, run_from, run_to, "edif"))
 254                 {
 255                         if (!edif_file.empty())
 256                                 Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
 257                 }
 258                 if (check_label(active, run_from, run_to, "blif"))
 259                 {
 260                         if (!blif_file.empty())
 261                                 Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
 262                 }
 263
 264                 log_pop();
 265         }
 266 } SynthXilinxPass;
 267
 268 PRIVATE_NAMESPACE_END