2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
25 static bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
27 if (label
== run_from
)
34 struct SynthXilinxPass
: public Pass
{
35 SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
38 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
40 log(" synth_xilinx [options]\n");
42 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
43 log("partly selected designs.\n");
45 log(" -top <module>\n");
46 log(" use the specified module as top module (default='top')\n");
48 log(" -arch <arch>\n");
49 log(" select architecture. the following architectures are supported:\n");
50 log(" spartan6 (default), artix7, kintex7, virtex7, zynq7000\n");
51 log(" (this parameter is not used by the command at the moment)\n");
53 log(" -edif <file>\n");
54 log(" write the design to the specified edif file. writing of an output file\n");
55 log(" is omitted if this parameter is not specified.\n");
57 log(" -run <from_label>:<to_label>\n");
58 log(" only run the commands between the labels (see below). an empty\n");
59 log(" from label is synonymous to 'begin', and empty to label is\n");
60 log(" synonymous to the end of the command list.\n");
63 log("The following commands are executed by this synthesis command:\n");
66 log(" hierarchy -check -top <top>\n");
85 log(" techmap -map <share_dir>/xilinx/cells.v\n");
89 log(" select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n");
90 log(" iopadmap -inpad BUFGP O:I @xilinx_clocks\n");
93 log(" select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %%x:+BUFGP[I] %%d\n");
94 log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
97 log(" write_edif -top <top> synth.edif\n");
100 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
102 std::string top_module
= "top";
103 std::string arch_name
= "spartan6";
104 std::string edif_file
;
105 std::string run_from
, run_to
;
108 for (argidx
= 1; argidx
< args
.size(); argidx
++)
110 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
111 top_module
= args
[++argidx
];
114 if (args
[argidx
] == "-arch" && argidx
+1 < args
.size()) {
115 arch_name
= args
[++argidx
];
118 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
119 edif_file
= args
[++argidx
];
122 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
123 size_t pos
= args
[argidx
+1].find(':');
124 if (pos
== std::string::npos
)
126 run_from
= args
[++argidx
].substr(0, pos
);
127 run_to
= args
[argidx
].substr(pos
+1);
132 extra_args(args
, argidx
, design
);
134 if (!design
->full_selection())
135 log_cmd_error("This comannd only operates on fully selected designs!\n");
137 if (arch_name
== "spartan6") {
140 if (arch_name
== "artix7") {
143 if (arch_name
== "kintex7") {
146 if (arch_name
== "zynq7000") {
149 log_cmd_error("Architecture '%s' is not supported!\n", arch_name
.c_str());
151 bool active
= run_from
.empty();
153 log_header("Executing SYNTH_XILINX pass.\n");
156 if (check_label(active
, run_from
, run_to
, "begin"))
158 Pass::call(design
, stringf("hierarchy -check -top %s", top_module
.c_str()));
161 if (check_label(active
, run_from
, run_to
, "coarse"))
163 Pass::call(design
, "proc");
164 Pass::call(design
, "opt");
165 Pass::call(design
, "memory");
166 Pass::call(design
, "clean");
167 Pass::call(design
, "fsm");
168 Pass::call(design
, "opt");
171 if (check_label(active
, run_from
, run_to
, "fine"))
173 Pass::call(design
, "techmap");
174 Pass::call(design
, "opt");
177 if (check_label(active
, run_from
, run_to
, "map_luts"))
179 Pass::call(design
, "abc -lut 6");
180 Pass::call(design
, "clean");
183 if (check_label(active
, run_from
, run_to
, "map_cells"))
185 Pass::call(design
, stringf("techmap -map %s", get_share_file_name("xilinx/cells.v").c_str()));
186 Pass::call(design
, "clean");
189 if (check_label(active
, run_from
, run_to
, "clkbuf"))
191 Pass::call(design
, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module
.c_str(), top_module
.c_str()));
192 Pass::call(design
, "iopadmap -inpad BUFGP O:I @xilinx_clocks");
195 if (check_label(active
, run_from
, run_to
, "iobuf"))
197 Pass::call(design
, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module
.c_str(), top_module
.c_str()));
198 Pass::call(design
, "iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
201 if (check_label(active
, run_from
, run_to
, "edif"))
203 if (!edif_file
.empty())
204 Pass::call(design
, stringf("write_edif -top %s %s", top_module
.c_str(), edif_file
.c_str()));