2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
30 if (label
== run_from
)
37 struct SynthXilinxPass
: public Pass
{
38 SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
41 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
43 log(" synth_xilinx [options]\n");
45 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
46 log("partly selected designs. At the moment this command creates netlists that are\n");
47 log("compatible with 7-Series Xilinx devices.\n");
49 log(" -top <module>\n");
50 log(" use the specified module as top module (default='top')\n");
52 log(" -edif <file>\n");
53 log(" write the design to the specified edif file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
56 log(" -run <from_label>:<to_label>\n");
57 log(" only run the commands between the labels (see below). an empty\n");
58 log(" from label is synonymous to 'begin', and empty to label is\n");
59 log(" synonymous to the end of the command list.\n");
62 log(" flatten design before synthesis\n");
65 log(" run 'abc' with -dff option\n");
68 log("The following commands are executed by this synthesis command:\n");
71 log(" read_verilog -lib +/xilinx/cells_sim.v\n");
72 log(" hierarchy -check -top <top>\n");
74 log(" flatten: (only if -flatten)\n");
79 log(" synth -run coarse\n");
83 log(" memory_bram -rules +/xilinx/brams.txt\n");
84 log(" techmap -map +/xilinx/brams_map.v\n");
87 log(" opt -fast -full\n");
90 log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
94 log(" abc -lut 5:8 [-dff]\n");
98 log(" techmap -map +/xilinx/cells_map.v\n");
102 log(" hierarchy -check\n");
104 log(" check -noinit\n");
107 log(" write_edif synth.edif\n");
110 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
112 std::string top_module
= "top";
113 std::string arch_name
= "spartan6";
114 std::string edif_file
;
115 std::string run_from
, run_to
;
116 bool flatten
= false;
120 for (argidx
= 1; argidx
< args
.size(); argidx
++)
122 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
123 top_module
= args
[++argidx
];
126 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
127 edif_file
= args
[++argidx
];
130 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
131 size_t pos
= args
[argidx
+1].find(':');
132 if (pos
== std::string::npos
)
134 run_from
= args
[++argidx
].substr(0, pos
);
135 run_to
= args
[argidx
].substr(pos
+1);
138 if (args
[argidx
] == "-flatten") {
142 if (args
[argidx
] == "-retime") {
148 extra_args(args
, argidx
, design
);
150 if (!design
->full_selection())
151 log_cmd_error("This comannd only operates on fully selected designs!\n");
153 bool active
= run_from
.empty();
155 log_header("Executing SYNTH_XILINX pass.\n");
158 if (check_label(active
, run_from
, run_to
, "begin"))
160 Pass::call(design
, "read_verilog -lib +/xilinx/cells_sim.v");
161 Pass::call(design
, stringf("hierarchy -check -top %s", top_module
.c_str()));
164 if (flatten
&& check_label(active
, run_from
, run_to
, "flatten"))
166 Pass::call(design
, "proc");
167 Pass::call(design
, "flatten");
170 if (check_label(active
, run_from
, run_to
, "coarse"))
172 Pass::call(design
, "synth -run coarse");
173 Pass::call(design
, "dff2dffe");
176 if (check_label(active
, run_from
, run_to
, "bram"))
178 Pass::call(design
, "memory_bram -rules +/xilinx/brams.txt");
179 Pass::call(design
, "techmap -map +/xilinx/brams_map.v");
182 if (check_label(active
, run_from
, run_to
, "fine"))
184 Pass::call(design
, "opt -fast -full");
185 Pass::call(design
, "memory_map");
186 Pass::call(design
, "opt -full");
187 Pass::call(design
, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
188 Pass::call(design
, "opt -fast");
191 if (check_label(active
, run_from
, run_to
, "map_luts"))
193 Pass::call(design
, "abc -lut 5:8" + string(retime
? " -dff" : ""));
194 Pass::call(design
, "clean");
197 if (check_label(active
, run_from
, run_to
, "map_cells"))
199 Pass::call(design
, "techmap -map +/xilinx/cells_map.v");
200 Pass::call(design
, "clean");
203 if (check_label(active
, run_from
, run_to
, "check"))
205 Pass::call(design
, "hierarchy -check");
206 Pass::call(design
, "stat");
207 Pass::call(design
, "check -noinit");
210 if (check_label(active
, run_from
, run_to
, "edif"))
212 if (!edif_file
.empty())
213 Pass::call(design
, stringf("write_edif %s", edif_file
.c_str()));
220 PRIVATE_NAMESPACE_END