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Add init support
[yosys.git] / techlibs / xilinx / synth_xilinx.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 #define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
30 // to one LUT6 (instead of a LUT5 + LUT2)
31
32 struct SynthXilinxPass : public ScriptPass
33 {
34 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
35
36 void help() YS_OVERRIDE
37 {
38 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
39 log("\n");
40 log(" synth_xilinx [options]\n");
41 log("\n");
42 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
43 log("partly selected designs. At the moment this command creates netlists that are\n");
44 log("compatible with 7-Series Xilinx devices.\n");
45 log("\n");
46 log(" -top <module>\n");
47 log(" use the specified module as top module\n");
48 log("\n");
49 log(" -family {xcup|xcu|xc7|xc6s}\n");
50 log(" run synthesis for the specified Xilinx architecture\n");
51 log(" generate the synthesis netlist for the specified family.\n");
52 log(" default: xc7\n");
53 log("\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
57 log("\n");
58 log(" -blif <file>\n");
59 log(" write the design to the specified BLIF file. writing of an output file\n");
60 log(" is omitted if this parameter is not specified.\n");
61 log("\n");
62 log(" -vpr\n");
63 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
64 log(" (this feature is experimental and incomplete)\n");
65 log("\n");
66 log(" -nobram\n");
67 log(" do not use block RAM cells in output netlist\n");
68 log("\n");
69 log(" -nolutram\n");
70 log(" do not use distributed RAM cells in output netlist\n");
71 log("\n");
72 log(" -nosrl\n");
73 log(" do not use distributed SRL cells in output netlist\n");
74 log("\n");
75 log(" -nocarry\n");
76 log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
77 log("\n");
78 log(" -nowidelut\n");
79 log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
80 log("\n");
81 log(" -widemux <int>\n");
82 log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
83 log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
84 log(" default: 0 (no inference)\n");
85 log("\n");
86 log(" -run <from_label>:<to_label>\n");
87 log(" only run the commands between the labels (see below). an empty\n");
88 log(" from label is synonymous to 'begin', and empty to label is\n");
89 log(" synonymous to the end of the command list.\n");
90 log("\n");
91 log(" -flatten\n");
92 log(" flatten design before synthesis\n");
93 log("\n");
94 log(" -retime\n");
95 log(" run 'abc' with -dff option\n");
96 log("\n");
97 log(" -abc9\n");
98 log(" use new ABC9 flow (EXPERIMENTAL)\n");
99 log("\n");
100 log("\n");
101 log("The following commands are executed by this synthesis command:\n");
102 help_script();
103 log("\n");
104 }
105
106 std::string top_opt, edif_file, blif_file, family;
107 bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
108 int widemux;
109
110 void clear_flags() YS_OVERRIDE
111 {
112 top_opt = "-auto-top";
113 edif_file.clear();
114 blif_file.clear();
115 family = "xc7";
116 flatten = false;
117 retime = false;
118 vpr = false;
119 nocarry = false;
120 nobram = false;
121 nolutram = false;
122 nosrl = false;
123 nocarry = false;
124 nowidelut = false;
125 abc9 = false;
126 widemux = 0;
127 }
128
129 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
130 {
131 std::string run_from, run_to;
132 clear_flags();
133
134 size_t argidx;
135 for (argidx = 1; argidx < args.size(); argidx++)
136 {
137 if (args[argidx] == "-top" && argidx+1 < args.size()) {
138 top_opt = "-top " + args[++argidx];
139 continue;
140 }
141 if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
142 family = args[++argidx];
143 continue;
144 }
145 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
146 edif_file = args[++argidx];
147 continue;
148 }
149 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
150 blif_file = args[++argidx];
151 continue;
152 }
153 if (args[argidx] == "-run" && argidx+1 < args.size()) {
154 size_t pos = args[argidx+1].find(':');
155 if (pos == std::string::npos)
156 break;
157 run_from = args[++argidx].substr(0, pos);
158 run_to = args[argidx].substr(pos+1);
159 continue;
160 }
161 if (args[argidx] == "-flatten") {
162 flatten = true;
163 continue;
164 }
165 if (args[argidx] == "-retime") {
166 retime = true;
167 continue;
168 }
169 if (args[argidx] == "-nocarry") {
170 nocarry = true;
171 continue;
172 }
173 if (args[argidx] == "-nowidelut") {
174 nowidelut = true;
175 continue;
176 }
177 if (args[argidx] == "-vpr") {
178 vpr = true;
179 continue;
180 }
181 if (args[argidx] == "-nocarry") {
182 nocarry = true;
183 continue;
184 }
185 if (args[argidx] == "-nobram") {
186 nobram = true;
187 continue;
188 }
189 if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
190 nolutram = true;
191 continue;
192 }
193 if (args[argidx] == "-nosrl") {
194 nosrl = true;
195 continue;
196 }
197 if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
198 widemux = atoi(args[++argidx].c_str());
199 continue;
200 }
201 if (args[argidx] == "-abc9") {
202 abc9 = true;
203 continue;
204 }
205 break;
206 }
207 extra_args(args, argidx, design);
208
209 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
210 log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
211
212 if (widemux != 0 && widemux < 2)
213 log_cmd_error("-widemux value must be 0 or >= 2.\n");
214
215 if (!design->full_selection())
216 log_cmd_error("This command only operates on fully selected designs!\n");
217
218 if (abc9 && retime)
219 log_cmd_error("-retime option not currently compatible with -abc9!\n");
220
221 log_header(design, "Executing SYNTH_XILINX pass.\n");
222 log_push();
223
224 run_script(design, run_from, run_to);
225
226 log_pop();
227 }
228
229 void script() YS_OVERRIDE
230 {
231 if (check_label("begin")) {
232 if (vpr)
233 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
234 else
235 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
236
237 run("read_verilog -lib +/xilinx/cells_xtra.v");
238
239 if (help_mode) {
240 run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
241 } else if (family == "xc6s") {
242 run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
243 } else if (family == "xc7") {
244 run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
245 }
246
247 run(stringf("hierarchy -check %s", top_opt.c_str()));
248 }
249
250 if (check_label("coarse")) {
251 run("proc");
252 if (help_mode || flatten)
253 run("flatten", "(if -flatten)");
254 run("opt_expr");
255 run("opt_clean");
256 run("check");
257 run("opt");
258 if (help_mode)
259 run("wreduce [-keepdc]", "(option for '-widemux')");
260 else
261 run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
262 run("peepopt");
263 run("opt_clean");
264
265 if (widemux > 0 || help_mode)
266 run("muxpack", " ('-widemux' only)");
267
268 // shregmap -tech xilinx can cope with $shiftx and $mux
269 // cells for identifying variable-length shift registers,
270 // so attempt to convert $pmux-es to the former
271 // Also: wide multiplexer inference benefits from this too
272 if (!(nosrl && widemux == 0) || help_mode) {
273 run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
274 run("clean", " (skip if '-nosrl' and '-widemux=0')");
275 }
276
277 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
278 run("alumacc");
279 run("share");
280 run("opt");
281 run("fsm");
282 run("opt -fast");
283 run("memory -nomap");
284 run("opt_clean");
285 }
286
287 if (check_label("map_bram", "(skip if '-nobram')")) {
288 if (help_mode) {
289 run("memory_bram -rules +/xilinx/{family}_brams.txt");
290 run("techmap -map +/xilinx/{family}_brams_map.v");
291 } else if (!nobram) {
292 if (family == "xc6s") {
293 run("memory_bram -rules +/xilinx/xc6s_brams.txt");
294 run("techmap -map +/xilinx/xc6s_brams_map.v");
295 } else if (family == "xc7") {
296 run("memory_bram -rules +/xilinx/xc7_brams.txt");
297 run("techmap -map +/xilinx/xc7_brams_map.v");
298 } else {
299 log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
300 }
301 }
302 }
303
304 if (check_label("map_lutram", "(skip if '-nolutram')")) {
305 if (!nolutram || help_mode) {
306 run("memory_bram -rules +/xilinx/lutrams.txt");
307 run("techmap -map +/xilinx/lutrams_map.v");
308 }
309 }
310
311 if (check_label("map_ffram")) {
312 if (widemux > 0)
313 run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
314 // performs less efficiently
315 else
316 run("opt -fast -full");
317 run("memory_map");
318 }
319
320 if (check_label("fine")) {
321 run("dffsr2dff");
322 run("dff2dffe");
323 if (help_mode) {
324 run("simplemap t:$mux", " ('-widemux' only)");
325 run("muxcover <internal options>, ('-widemux' only)");
326 }
327 else if (widemux > 0) {
328 run("simplemap t:$mux");
329 constexpr int cost_mux2 = 100;
330 std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
331 switch (widemux) {
332 case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
333 case 3:
334 case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
335 case 5:
336 case 6:
337 case 7:
338 case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
339 case 9:
340 case 10:
341 case 11:
342 case 12:
343 case 13:
344 case 14:
345 case 15:
346 default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
347 }
348 run("muxcover " + muxcover_args);
349 }
350 run("opt -full");
351
352 if (!nosrl || help_mode) {
353 // shregmap operates on bit-level flops, not word-level,
354 // so break those down here
355 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
356 // shregmap with '-tech xilinx' infers variable length shift regs
357 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
358 }
359
360 std::string techmap_args = " -map +/techmap.v";
361 if (help_mode)
362 techmap_args += " [-map +/xilinx/mux_map.v]";
363 else if (widemux > 0)
364 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
365 if (help_mode)
366 techmap_args += " [-map +/xilinx/arith_map.v]";
367 else if (!nocarry) {
368 techmap_args += " -map +/xilinx/arith_map.v";
369 if (vpr)
370 techmap_args += " -D _EXPLICIT_CARRY";
371 else if (abc9)
372 techmap_args += " -D _CLB_CARRY";
373 }
374 run("techmap " + techmap_args);
375 run("opt -fast");
376 }
377
378 if (check_label("map_cells")) {
379 std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
380 if (widemux > 0)
381 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
382 run("techmap " + techmap_args);
383 run("clean");
384 }
385
386 if (check_label("map_luts")) {
387 run("opt_expr -mux_undef");
388 if (help_mode)
389 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
390 else if (abc9) {
391 if (family != "xc7")
392 log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
393 if (nowidelut)
394 run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
395 else
396 run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
397 }
398 else {
399 if (nowidelut)
400 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
401 else
402 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
403 }
404 run("clean");
405
406 // This shregmap call infers fixed length shift registers after abc
407 // has performed any necessary retiming
408 if (!nosrl || help_mode)
409 run("xilinx_srl -minlen 3", "(skip if '-nosrl')");
410 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
411 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
412 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
413 run("clean");
414 }
415
416 if (check_label("check")) {
417 run("hierarchy -check");
418 run("stat -tech xilinx");
419 run("check -noinit");
420 }
421
422 if (check_label("edif")) {
423 if (!edif_file.empty() || help_mode)
424 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
425 }
426
427 if (check_label("blif")) {
428 if (!blif_file.empty() || help_mode)
429 run(stringf("write_blif %s", edif_file.c_str()));
430 }
431 }
432 } SynthXilinxPass;
433
434 PRIVATE_NAMESPACE_END