techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthXilinxPass : public ScriptPass
  29 {
  30         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_xilinx [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  39                 log("partly selected designs. At the moment this command creates netlists that are\n");
  40                 log("compatible with 7-Series Xilinx devices.\n");
  41                 log("\n");
  42                 log("    -top <module>\n");
  43                 log("        use the specified module as top module\n");
  44                 log("\n");
  45                 log("    -family {xcup|xcu|xc7|xc6s}\n");
  46                 log("        run synthesis for the specified Xilinx architecture\n");
  47                 log("        generate the synthesis netlist for the specified family.\n");
  48                 log("        default: xc7\n");
  49                 log("\n");
  50                 log("    -edif <file>\n");
  51                 log("        write the design to the specified edif file. writing of an output file\n");
  52                 log("        is omitted if this parameter is not specified.\n");
  53                 log("\n");
  54                 log("    -blif <file>\n");
  55                 log("        write the design to the specified BLIF file. writing of an output file\n");
  56                 log("        is omitted if this parameter is not specified.\n");
  57                 log("\n");
  58                 log("    -vpr\n");
  59                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  60                 log("        (this feature is experimental and incomplete)\n");
  61                 log("\n");
  62                 log("    -nobram\n");
  63                 log("        disable inference of block rams\n");
  64                 log("\n");
  65                 log("    -nodram\n");
  66                 log("        disable inference of distributed rams\n");
  67                 log("\n");
  68                 log("    -nosrl\n");
  69                 log("        disable inference of shift registers\n");
  70                 log("\n");
  71                 log("    -nocarry\n");
  72                 log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
  73                 log("\n");
  74                 log("    -nowidelut\n");
  75                 log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
  76                 log("\n");
  77                 log("    -run <from_label>:<to_label>\n");
  78                 log("        only run the commands between the labels (see below). an empty\n");
  79                 log("        from label is synonymous to 'begin', and empty to label is\n");
  80                 log("        synonymous to the end of the command list.\n");
  81                 log("\n");
  82                 log("    -flatten\n");
  83                 log("        flatten design before synthesis\n");
  84                 log("\n");
  85                 log("    -retime\n");
  86                 log("        run 'abc' with -dff option\n");
  87                 log("\n");
  88                 log("\n");
  89                 log("The following commands are executed by this synthesis command:\n");
  90                 help_script();
  91                 log("\n");
  92         }
  93
  94         std::string top_opt, edif_file, blif_file, family;
  95         bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut;
  96
  97         void clear_flags() YS_OVERRIDE
  98         {
  99                 top_opt = "-auto-top";
 100                 edif_file.clear();
 101                 blif_file.clear();
 102                 flatten = false;
 103                 retime = false;
 104                 vpr = false;
 105                 nobram = false;
 106                 nodram = false;
 107                 nosrl = false;
 108                 nocarry = false;
 109                 nowidelut = false;
 110                 family = "xc7";
 111         }
 112
 113         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 114         {
 115                 std::string run_from, run_to;
 116                 clear_flags();
 117
 118                 size_t argidx;
 119                 for (argidx = 1; argidx < args.size(); argidx++)
 120                 {
 121                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 122                                 top_opt = "-top " + args[++argidx];
 123                                 continue;
 124                         }
 125                         if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
 126                                 family = args[++argidx];
 127                                 continue;
 128                         }
 129                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 130                                 edif_file = args[++argidx];
 131                                 continue;
 132                         }
 133                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 134                                 blif_file = args[++argidx];
 135                                 continue;
 136                         }
 137                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 138                                 size_t pos = args[argidx+1].find(':');
 139                                 if (pos == std::string::npos)
 140                                         break;
 141                                 run_from = args[++argidx].substr(0, pos);
 142                                 run_to = args[argidx].substr(pos+1);
 143                                 continue;
 144                         }
 145                         if (args[argidx] == "-flatten") {
 146                                 flatten = true;
 147                                 continue;
 148                         }
 149                         if (args[argidx] == "-retime") {
 150                                 retime = true;
 151                                 continue;
 152                         }
 153                         if (args[argidx] == "-nocarry") {
 154                                 nocarry = true;
 155                                 continue;
 156                         }
 157                         if (args[argidx] == "-nowidelut") {
 158                                 nowidelut = true;
 159                                 continue;
 160                         }
 161                         if (args[argidx] == "-vpr") {
 162                                 vpr = true;
 163                                 continue;
 164                         }
 165                         if (args[argidx] == "-nobram") {
 166                                 nobram = true;
 167                                 continue;
 168                         }
 169                         if (args[argidx] == "-nodram") {
 170                                 nodram = true;
 171                                 continue;
 172                         }
 173                         if (args[argidx] == "-nosrl") {
 174                                 nosrl = true;
 175                                 continue;
 176                         }
 177                         break;
 178                 }
 179                 extra_args(args, argidx, design);
 180
 181                 if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
 182                         log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
 183
 184                 if (!design->full_selection())
 185                         log_cmd_error("This command only operates on fully selected designs!\n");
 186
 187                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 188                 log_push();
 189
 190                 run_script(design, run_from, run_to);
 191
 192                 log_pop();
 193         }
 194
 195         void script() YS_OVERRIDE
 196         {
 197                 if (check_label("begin")) {
 198                         if (vpr)
 199                                 run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 200                         else
 201                                 run("read_verilog -lib +/xilinx/cells_sim.v");
 202
 203                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 204
 205                         if (!nobram || help_mode)
 206                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 207
 208                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 209                 }
 210
 211                 if (check_label("flatten", "(with '-flatten' only)")) {
 212                         if (flatten || help_mode) {
 213                                 run("proc");
 214                                 run("flatten");
 215                         }
 216                 }
 217
 218                 if (check_label("coarse")) {
 219                         run("synth -run coarse");
 220                 }
 221
 222                 if (check_label("bram", "(skip if '-nobram')")) {
 223                         if (!nobram || help_mode) {
 224                                 run("memory_bram -rules +/xilinx/brams.txt");
 225                                 run("techmap -map +/xilinx/brams_map.v");
 226                         }
 227                 }
 228
 229                 if (check_label("dram", "(skip if '-nodram')")) {
 230                         if (!nodram || help_mode) {
 231                                 run("memory_bram -rules +/xilinx/drams.txt");
 232                                 run("techmap -map +/xilinx/drams_map.v");
 233                         }
 234                 }
 235
 236                 if (check_label("fine")) {
 237                         // shregmap -tech xilinx can cope with $shiftx and $mux
 238                         //   cells for identifiying variable-length shift registers,
 239                         //   so attempt to convert $pmux-es to the former
 240                         if (!nosrl || help_mode)
 241                                 run("pmux2shiftx", "(skip if '-nosrl')");
 242
 243                         run("opt -fast -full");
 244                         run("memory_map");
 245                         run("dffsr2dff");
 246                         run("dff2dffe");
 247                         run("opt -full");
 248
 249                         if (!nosrl || help_mode) {
 250                                 // shregmap operates on bit-level flops, not word-level,
 251                                 //   so break those down here
 252                                 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 253                                 // shregmap with '-tech xilinx' infers variable length shift regs
 254                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 255                         }
 256
 257                         if (help_mode)
 258                                 run("techmap -map +/techmap.v [-map +/xilinx/arith_map.v]", "(skip if '-nocarry')");
 259                         else if (!nocarry) {
 260                                 if (!vpr)
 261                                         run("techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 262                                 else
 263                                         run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
 264                         }
 265
 266                         run("opt -fast");
 267                 }
 268
 269                 if (check_label("map_cells")) {
 270                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 271                         run("clean");
 272                 }
 273
 274                 if (check_label("map_luts")) {
 275                         if (help_mode)
 276                                 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
 277                         else if (nowidelut)
 278                                 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 279                         else
 280                                 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 281                         run("clean");
 282                         // This shregmap call infers fixed length shift registers after abc
 283                         //   has performed any necessary retiming
 284                         if (!nosrl || help_mode)
 285                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 286                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 287                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 288                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 289                         run("clean");
 290                 }
 291
 292                 if (check_label("check")) {
 293                         run("hierarchy -check");
 294                         run("stat -tech xilinx");
 295                         run("check -noinit");
 296                 }
 297
 298                 if (check_label("edif")) {
 299                         if (!edif_file.empty() || help_mode)
 300                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 301                 }
 302
 303                 if (check_label("blif")) {
 304                         if (!blif_file.empty() || help_mode)
 305                                 run(stringf("write_blif %s", edif_file.c_str()));
 306                 }
 307         }
 308 } SynthXilinxPass;
 309
 310 PRIVATE_NAMESPACE_END