techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
  29                              // to one LUT6 (instead of a LUT5 + LUT2)
  30
  31 struct SynthXilinxPass : public ScriptPass
  32 {
  33         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  34
  35         void help() YS_OVERRIDE
  36         {
  37                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  38                 log("\n");
  39                 log("    synth_xilinx [options]\n");
  40                 log("\n");
  41                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  42                 log("partly selected designs. At the moment this command creates netlists that are\n");
  43                 log("compatible with 7-Series Xilinx devices.\n");
  44                 log("\n");
  45                 log("    -top <module>\n");
  46                 log("        use the specified module as top module\n");
  47                 log("\n");
  48                 log("    -arch {xcup|xcu|xc7|xc6s}\n");
  49                 log("        run synthesis for the specified Xilinx architecture\n");
  50                 log("        default: xc7\n");
  51                 log("\n");
  52                 log("    -edif <file>\n");
  53                 log("        write the design to the specified edif file. writing of an output file\n");
  54                 log("        is omitted if this parameter is not specified.\n");
  55                 log("\n");
  56                 log("    -blif <file>\n");
  57                 log("        write the design to the specified BLIF file. writing of an output file\n");
  58                 log("        is omitted if this parameter is not specified.\n");
  59                 log("\n");
  60                 log("    -vpr\n");
  61                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  62                 log("        (this feature is experimental and incomplete)\n");
  63                 log("\n");
  64                 log("    -nocarry\n");
  65                 log("        disable inference of carry chains\n");
  66                 log("\n");
  67                 log("    -nobram\n");
  68                 log("        disable inference of block rams\n");
  69                 log("\n");
  70                 log("    -nodram\n");
  71                 log("        disable inference of distributed rams\n");
  72                 log("\n");
  73                 log("    -nosrl\n");
  74                 log("        disable inference of shift registers\n");
  75                 log("\n");
  76                 log("    -nomux\n");
  77                 log("        disable inference of wide multiplexers\n");
  78                 log("\n");
  79                 log("    -run <from_label>:<to_label>\n");
  80                 log("        only run the commands between the labels (see below). an empty\n");
  81                 log("        from label is synonymous to 'begin', and empty to label is\n");
  82                 log("        synonymous to the end of the command list.\n");
  83                 log("\n");
  84                 log("    -flatten\n");
  85                 log("        flatten design before synthesis\n");
  86                 log("\n");
  87                 log("    -retime\n");
  88                 log("        run 'abc' with -dff option\n");
  89                 log("\n");
  90                 log("    -abc9\n");
  91                 log("        use new ABC9 flow (EXPERIMENTAL)\n");
  92                 log("\n");
  93                 log("\n");
  94                 log("The following commands are executed by this synthesis command:\n");
  95                 help_script();
  96                 log("\n");
  97         }
  98
  99         std::string top_opt, edif_file, blif_file, abc, arch;
 100         bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
 101
 102         void clear_flags() YS_OVERRIDE
 103         {
 104                 top_opt = "-auto-top";
 105                 edif_file.clear();
 106                 blif_file.clear();
 107                 abc = "abc";
 108                 flatten = false;
 109                 retime = false;
 110                 vpr = false;
 111                 nocarry = false;
 112                 nobram = false;
 113                 nodram = false;
 114                 nosrl = false;
 115                 nomux = false;
 116                 arch = "xc7";
 117         }
 118
 119         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 120         {
 121                 std::string run_from, run_to;
 122                 clear_flags();
 123
 124                 size_t argidx;
 125                 for (argidx = 1; argidx < args.size(); argidx++)
 126                 {
 127                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 128                                 top_opt = "-top " + args[++argidx];
 129                                 continue;
 130                         }
 131                         if (args[argidx] == "-arch" && argidx+1 < args.size()) {
 132                                 arch = args[++argidx];
 133                                 continue;
 134                         }
 135                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 136                                 edif_file = args[++argidx];
 137                                 continue;
 138                         }
 139                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 140                                 blif_file = args[++argidx];
 141                                 continue;
 142                         }
 143                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 144                                 size_t pos = args[argidx+1].find(':');
 145                                 if (pos == std::string::npos)
 146                                         break;
 147                                 run_from = args[++argidx].substr(0, pos);
 148                                 run_to = args[argidx].substr(pos+1);
 149                                 continue;
 150                         }
 151                         if (args[argidx] == "-flatten") {
 152                                 flatten = true;
 153                                 continue;
 154                         }
 155                         if (args[argidx] == "-retime") {
 156                                 retime = true;
 157                                 continue;
 158                         }
 159                         if (args[argidx] == "-vpr") {
 160                                 vpr = true;
 161                                 continue;
 162                         }
 163                         if (args[argidx] == "-nocarry") {
 164                                 nocarry = true;
 165                                 continue;
 166                         }
 167                         if (args[argidx] == "-nobram") {
 168                                 nobram = true;
 169                                 continue;
 170                         }
 171                         if (args[argidx] == "-nodram") {
 172                                 nodram = true;
 173                                 continue;
 174                         }
 175                         if (args[argidx] == "-nosrl") {
 176                                 nosrl = true;
 177                                 continue;
 178                         }
 179                         if (args[argidx] == "-nomux") {
 180                                 nomux = true;
 181                                 continue;
 182                         }
 183                         if (args[argidx] == "-abc9") {
 184                                 abc = "abc9";
 185                                 continue;
 186                         }
 187                         break;
 188                 }
 189                 extra_args(args, argidx, design);
 190
 191                 if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
 192                         log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
 193
 194                 if (!design->full_selection())
 195                         log_cmd_error("This command only operates on fully selected designs!\n");
 196
 197                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 198                 log_push();
 199
 200                 run_script(design, run_from, run_to);
 201
 202                 log_pop();
 203         }
 204
 205         void script() YS_OVERRIDE
 206         {
 207                 if (check_label("begin")) {
 208                         if (vpr)
 209                                 run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 210                         else
 211                                 run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 212
 213                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 214
 215                         if (!nobram || help_mode)
 216                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 217
 218                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 219                 }
 220
 221                 if (check_label("coarse")) {
 222                         run("proc");
 223                         if (flatten || help_mode)
 224                                 run("flatten", "(with -flatten only)");
 225                         run("opt_expr");
 226                         run("opt_clean");
 227                         run("check");
 228                         run("opt");
 229                         // FIXME
 230                         //run("wreduce");
 231                         run("peepopt");
 232                         run("opt_clean");
 233                         run("alumacc");
 234                         run("share");
 235                         run("opt");
 236                         run("fsm");
 237                         run("opt -fast");
 238                         run("memory -nomap");
 239                         run("opt_clean");
 240
 241                         //if (!nomux || help_mode)
 242                         //      run("muxpack", "(skip if '-nomux')");
 243
 244                         // shregmap -tech xilinx can cope with $shiftx and $mux
 245                         //   cells for identifying variable-length shift registers,
 246                         //   so attempt to convert $pmux-es to the former
 247                         // Also: wide multiplexer inference benefits from this too
 248                         if (!(nosrl && nomux) || help_mode)
 249                                 run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
 250
 251                         // Run a number of peephole optimisations, including one
 252                         //   that optimises $mul cells driving $shiftx's B input
 253                         //   and that aids wide mux analysis
 254                         run("peepopt");
 255                 }
 256
 257                 if (check_label("bram", "(skip if '-nobram')")) {
 258                         if (!nobram || help_mode) {
 259                                 run("memory_bram -rules +/xilinx/brams.txt");
 260                                 run("techmap -map +/xilinx/brams_map.v");
 261                         }
 262                 }
 263
 264                 if (check_label("dram", "(skip if '-nodram')")) {
 265                         if (!nodram || help_mode) {
 266                                 run("memory_bram -rules +/xilinx/drams.txt");
 267                                 run("techmap -map +/xilinx/drams_map.v");
 268                         }
 269                 }
 270
 271                 if (check_label("fine")) {
 272                         run("opt -fast");
 273                         run("memory_map");
 274                         run("dffsr2dff");
 275                         run("dff2dffe");
 276                         if (!nomux || help_mode) {
 277                                 run("simplemap t:$mux", "                               (skip if -nomux)");
 278                                               // FIXME: Must specify mux4, even if we don't need it,
 279                                               //        otherwise it will use mux8 as mux4
 280                                 run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
 281                         }
 282                         run("opt -full");
 283
 284                         if (!nosrl || help_mode) {
 285                                 // shregmap operates on bit-level flops, not word-level,
 286                                 //   so break those down here
 287                                 run("simplemap t:$dff t:$dffe", "       (skip if '-nosrl')");
 288                                 // shregmap with '-tech xilinx' infers variable length shift regs
 289                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 290                         }
 291
 292                         std::string techmap_files = " -map +/techmap.v";
 293                         if (help_mode)
 294                                 techmap_files += " [-map +/xilinx/mux_map.v]";
 295                         else if (!nomux)
 296                                 techmap_files += " -map +/xilinx/mux_map.v";
 297                         if (help_mode)
 298                                 techmap_files += " [-map +/xilinx/arith_map.v]";
 299                         else if (!nocarry) {
 300                                 techmap_files += " -map +/xilinx/arith_map.v";
 301                                 if (vpr)
 302                                         techmap_files += " -D _EXPLICIT_CARRY";
 303                                 else if (abc == "abc9")
 304                                         techmap_files += " -D _CLB_CARRY";
 305                         }
 306                         run("techmap " + techmap_files);
 307                         run("opt -fast");
 308                 }
 309
 310                 if (check_label("map_cells")) {
 311                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 312                         run("clean");
 313                 }
 314
 315                 if (check_label("map_luts")) {
 316                         run("opt_expr -mux_undef");
 317                         if (abc == "abc9")
 318                                 run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
 319                         else if (help_mode)
 320                                 run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 321                         else
 322                                 run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 323                         run("clean");
 324
 325                         // This shregmap call infers fixed length shift registers after abc
 326                         //   has performed any necessary retiming
 327                         if (!nosrl || help_mode)
 328                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 329                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 330                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 331                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 332                         run("clean");
 333                 }
 334
 335                 if (check_label("check")) {
 336                         run("hierarchy -check");
 337                         run("stat -tech xilinx");
 338                         run("check -noinit");
 339                 }
 340
 341                 if (check_label("edif")) {
 342                         if (!edif_file.empty() || help_mode)
 343                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 344                 }
 345
 346                 if (check_label("blif")) {
 347                         if (!blif_file.empty() || help_mode)
 348                                 run(stringf("write_blif %s", edif_file.c_str()));
 349                 }
 350         }
 351 } SynthXilinxPass;
 352
 353 PRIVATE_NAMESPACE_END