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1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
29 // to one LUT6 (instead of a LUT5 + LUT2)
30
31 struct SynthXilinxPass : public ScriptPass
32 {
33 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
34
35 void help() YS_OVERRIDE
36 {
37 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
38 log("\n");
39 log(" synth_xilinx [options]\n");
40 log("\n");
41 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
42 log("partly selected designs. At the moment this command creates netlists that are\n");
43 log("compatible with 7-Series Xilinx devices.\n");
44 log("\n");
45 log(" -top <module>\n");
46 log(" use the specified module as top module\n");
47 log("\n");
48 log(" -arch {xcup|xcu|xc7|xc6s}\n");
49 log(" run synthesis for the specified Xilinx architecture\n");
50 log(" default: xc7\n");
51 log("\n");
52 log(" -edif <file>\n");
53 log(" write the design to the specified edif file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
55 log("\n");
56 log(" -blif <file>\n");
57 log(" write the design to the specified BLIF file. writing of an output file\n");
58 log(" is omitted if this parameter is not specified.\n");
59 log("\n");
60 log(" -vpr\n");
61 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
62 log(" (this feature is experimental and incomplete)\n");
63 log("\n");
64 log(" -nocarry\n");
65 log(" disable inference of carry chains\n");
66 log("\n");
67 log(" -nobram\n");
68 log(" disable inference of block rams\n");
69 log("\n");
70 log(" -nodram\n");
71 log(" disable inference of distributed rams\n");
72 log("\n");
73 log(" -nosrl\n");
74 log(" disable inference of shift registers\n");
75 log("\n");
76 log(" -minmuxf <int>\n");
77 log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
78 log(" above this number of inputs (minimum value 5).\n");
79 log(" default: 0 (no inference)\n");
80 log("\n");
81 log(" -run <from_label>:<to_label>\n");
82 log(" only run the commands between the labels (see below). an empty\n");
83 log(" from label is synonymous to 'begin', and empty to label is\n");
84 log(" synonymous to the end of the command list.\n");
85 log("\n");
86 log(" -flatten\n");
87 log(" flatten design before synthesis\n");
88 log("\n");
89 log(" -retime\n");
90 log(" run 'abc' with -dff option\n");
91 log("\n");
92 log(" -abc9\n");
93 log(" use new ABC9 flow (EXPERIMENTAL)\n");
94 log("\n");
95 log("\n");
96 log("The following commands are executed by this synthesis command:\n");
97 help_script();
98 log("\n");
99 }
100
101 std::string top_opt, edif_file, blif_file, abc, arch;
102 bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
103 int minmuxf;
104
105 void clear_flags() YS_OVERRIDE
106 {
107 top_opt = "-auto-top";
108 edif_file.clear();
109 blif_file.clear();
110 abc = "abc";
111 flatten = false;
112 retime = false;
113 vpr = false;
114 nocarry = false;
115 nobram = false;
116 nodram = false;
117 nosrl = false;
118 arch = "xc7";
119 minmuxf = 0;
120 }
121
122 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
123 {
124 std::string run_from, run_to;
125 clear_flags();
126
127 size_t argidx;
128 for (argidx = 1; argidx < args.size(); argidx++)
129 {
130 if (args[argidx] == "-top" && argidx+1 < args.size()) {
131 top_opt = "-top " + args[++argidx];
132 continue;
133 }
134 if (args[argidx] == "-arch" && argidx+1 < args.size()) {
135 arch = args[++argidx];
136 continue;
137 }
138 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
139 edif_file = args[++argidx];
140 continue;
141 }
142 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
143 blif_file = args[++argidx];
144 continue;
145 }
146 if (args[argidx] == "-run" && argidx+1 < args.size()) {
147 size_t pos = args[argidx+1].find(':');
148 if (pos == std::string::npos)
149 break;
150 run_from = args[++argidx].substr(0, pos);
151 run_to = args[argidx].substr(pos+1);
152 continue;
153 }
154 if (args[argidx] == "-flatten") {
155 flatten = true;
156 continue;
157 }
158 if (args[argidx] == "-retime") {
159 retime = true;
160 continue;
161 }
162 if (args[argidx] == "-vpr") {
163 vpr = true;
164 continue;
165 }
166 if (args[argidx] == "-nocarry") {
167 nocarry = true;
168 continue;
169 }
170 if (args[argidx] == "-nobram") {
171 nobram = true;
172 continue;
173 }
174 if (args[argidx] == "-nodram") {
175 nodram = true;
176 continue;
177 }
178 if (args[argidx] == "-nosrl") {
179 nosrl = true;
180 continue;
181 }
182 if (args[argidx] == "-minmuxf" && argidx+1 < args.size()) {
183 minmuxf = atoi(args[++argidx].c_str());
184 continue;
185 }
186 if (args[argidx] == "-abc9") {
187 abc = "abc9";
188 continue;
189 }
190 break;
191 }
192 extra_args(args, argidx, design);
193
194 if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
195 log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
196
197 if (minmuxf != 0 && minmuxf < 5)
198 log_cmd_error("-minmuxf value must be 0 or >= 5.\n");
199
200 if (!design->full_selection())
201 log_cmd_error("This command only operates on fully selected designs!\n");
202
203 log_header(design, "Executing SYNTH_XILINX pass.\n");
204 log_push();
205
206 run_script(design, run_from, run_to);
207
208 log_pop();
209 }
210
211 void script() YS_OVERRIDE
212 {
213 if (check_label("begin")) {
214 if (vpr)
215 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
216 else
217 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
218
219 run("read_verilog -lib +/xilinx/cells_xtra.v");
220
221 if (!nobram || help_mode)
222 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
223
224 run(stringf("hierarchy -check %s", top_opt.c_str()));
225 }
226
227 if (check_label("coarse")) {
228 run("proc");
229 if (flatten || help_mode)
230 run("flatten", "(with -flatten only)");
231 run("opt_expr");
232 run("opt_clean");
233 run("check");
234 run("opt");
235 if (help_mode)
236 run("wreduce [c:* t:$mux %d]", "(selection for '-minmuxf' only)");
237 else
238 run("wreduce" + std::string(minmuxf > 0 ? " c:* t:$mux %d" : ""));
239 run("peepopt");
240 run("opt_clean");
241 run("alumacc");
242 run("share");
243 run("opt");
244 run("fsm");
245 run("opt -fast");
246 run("memory -nomap");
247 run("opt_clean");
248
249 if (minmuxf > 0 || help_mode)
250 run("muxpack", " ('-minmuxf' only)");
251
252 // shregmap -tech xilinx can cope with $shiftx and $mux
253 // cells for identifying variable-length shift registers,
254 // so attempt to convert $pmux-es to the former
255 // Also: wide multiplexer inference benefits from this too
256 if (!(nosrl && minmuxf == 0) || help_mode)
257 run("pmux2shiftx", "(skip if '-nosrl' and '-minmuxf' < 5)");
258 }
259
260 if (check_label("bram", "(skip if '-nobram')")) {
261 if (!nobram || help_mode) {
262 run("memory_bram -rules +/xilinx/brams.txt");
263 run("techmap -map +/xilinx/brams_map.v");
264 }
265 }
266
267 if (check_label("dram", "(skip if '-nodram')")) {
268 if (!nodram || help_mode) {
269 run("memory_bram -rules +/xilinx/drams.txt");
270 run("techmap -map +/xilinx/drams_map.v");
271 }
272 }
273
274 if (check_label("fine")) {
275 run("opt -fast");
276 run("memory_map");
277 run("dffsr2dff");
278 run("dff2dffe");
279 if (minmuxf > 0 || help_mode) {
280 run("simplemap t:$mux", " ('-minmuxf' only)");
281 if (minmuxf > 0 || help_mode) {
282 std::string muxcover_args = " -dmux=0";
283 switch (minmuxf) {
284 // NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
285 // of those so that 4:1 muxes and below are implemented
286 // out of mux2s
287 case 5: muxcover_args += " -mux8=350 -mux16=400"; break;
288 case 6: muxcover_args += " -mux8=450 -mux16=500"; break;
289 case 7: muxcover_args += " -mux8=550 -mux16=600"; break;
290 case 8: muxcover_args += " -mux8=650 -mux16=700"; break;
291 case 9: muxcover_args += " -mux16=750"; break;
292 case 10: muxcover_args += " -mux16=850"; break;
293 case 11: muxcover_args += " -mux16=950"; break;
294 case 12: muxcover_args += " -mux16=1050"; break;
295 case 13: muxcover_args += " -mux16=1150"; break;
296 case 14: muxcover_args += " -mux16=1250"; break;
297 case 15: muxcover_args += " -mux16=1350"; break;
298 default: muxcover_args += " -mux16=1450"; break;
299 }
300 run("muxcover " + muxcover_args, "('-minmuxf' only)");
301 }
302 }
303 run("opt -full");
304
305 if (!nosrl || help_mode) {
306 // shregmap operates on bit-level flops, not word-level,
307 // so break those down here
308 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
309 // shregmap with '-tech xilinx' infers variable length shift regs
310 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
311 }
312
313 std::string techmap_args = " -map +/techmap.v";
314 if (help_mode)
315 techmap_args += " [-map +/xilinx/mux_map.v]";
316 else if (minmuxf > 0)
317 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", minmuxf);
318 if (help_mode)
319 techmap_args += " [-map +/xilinx/arith_map.v]";
320 else if (!nocarry) {
321 techmap_args += " -map +/xilinx/arith_map.v";
322 if (vpr)
323 techmap_args += " -D _EXPLICIT_CARRY";
324 else if (abc == "abc9")
325 techmap_args += " -D _CLB_CARRY";
326 }
327 run("techmap " + techmap_args);
328 run("opt -fast");
329 }
330
331 if (check_label("map_cells")) {
332 std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
333 if (minmuxf > 0)
334 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", minmuxf);
335 run("techmap " + techmap_args);
336 run("clean");
337 }
338
339 if (check_label("map_luts")) {
340 run("opt_expr -mux_undef");
341 if (abc == "abc9")
342 run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
343 else if (help_mode)
344 run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
345 else
346 run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
347 run("clean");
348
349 // This shregmap call infers fixed length shift registers after abc
350 // has performed any necessary retiming
351 if (!nosrl || help_mode)
352 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
353 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
354 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
355 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
356 run("clean");
357 }
358
359 if (check_label("check")) {
360 run("hierarchy -check");
361 run("stat -tech xilinx");
362 run("check -noinit");
363 }
364
365 if (check_label("edif")) {
366 if (!edif_file.empty() || help_mode)
367 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
368 }
369
370 if (check_label("blif")) {
371 if (!blif_file.empty() || help_mode)
372 run(stringf("write_blif %s", edif_file.c_str()));
373 }
374 }
375 } SynthXilinxPass;
376
377 PRIVATE_NAMESPACE_END