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Merge remote-tracking branch 'origin/xaig' into xc7mux
[yosys.git] / techlibs / xilinx / synth_xilinx.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
29 // to one LUT6 (instead of a LUT5 + LUT2)
30
31 struct SynthXilinxPass : public ScriptPass
32 {
33 SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
34
35 void help() YS_OVERRIDE
36 {
37 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
38 log("\n");
39 log(" synth_xilinx [options]\n");
40 log("\n");
41 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
42 log("partly selected designs. At the moment this command creates netlists that are\n");
43 log("compatible with 7-Series Xilinx devices.\n");
44 log("\n");
45 log(" -top <module>\n");
46 log(" use the specified module as top module\n");
47 log("\n");
48 log(" -arch {xcup|xcu|xc7|xc6s}\n");
49 log(" run synthesis for the specified Xilinx architecture\n");
50 log(" default: xc7\n");
51 log("\n");
52 log(" -edif <file>\n");
53 log(" write the design to the specified edif file. writing of an output file\n");
54 log(" is omitted if this parameter is not specified.\n");
55 log("\n");
56 log(" -blif <file>\n");
57 log(" write the design to the specified BLIF file. writing of an output file\n");
58 log(" is omitted if this parameter is not specified.\n");
59 log("\n");
60 log(" -vpr\n");
61 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
62 log(" (this feature is experimental and incomplete)\n");
63 log("\n");
64 log(" -nocarry\n");
65 log(" disable inference of carry chains\n");
66 log("\n");
67 log(" -nobram\n");
68 log(" disable inference of block rams\n");
69 log("\n");
70 log(" -nodram\n");
71 log(" disable inference of distributed rams\n");
72 log("\n");
73 log(" -nosrl\n");
74 log(" disable inference of shift registers\n");
75 log("\n");
76 log(" -nocarry\n");
77 log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
78 log("\n");
79 log(" -nowidelut\n");
80 log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
81 log("\n");
82 log(" -widemux <int>\n");
83 log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
84 log(" above this number of inputs (minimum value 5).\n");
85 log(" default: 0 (no inference)\n");
86 log("\n");
87 log(" -run <from_label>:<to_label>\n");
88 log(" only run the commands between the labels (see below). an empty\n");
89 log(" from label is synonymous to 'begin', and empty to label is\n");
90 log(" synonymous to the end of the command list.\n");
91 log("\n");
92 log(" -flatten\n");
93 log(" flatten design before synthesis\n");
94 log("\n");
95 log(" -retime\n");
96 log(" run 'abc' with -dff option\n");
97 log("\n");
98 log(" -abc9\n");
99 log(" use new ABC9 flow (EXPERIMENTAL)\n");
100 log("\n");
101 log("\n");
102 log("The following commands are executed by this synthesis command:\n");
103 help_script();
104 log("\n");
105 }
106
107 std::string top_opt, edif_file, blif_file, arch;
108 bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
109 int widemux;
110
111 void clear_flags() YS_OVERRIDE
112 {
113 top_opt = "-auto-top";
114 edif_file.clear();
115 blif_file.clear();
116 arch = "xc7";
117 flatten = false;
118 retime = false;
119 vpr = false;
120 nocarry = false;
121 nobram = false;
122 nodram = false;
123 nosrl = false;
124 nocarry = false;
125 nowidelut = false;
126 abc9 = false;
127 widemux = 0;
128 }
129
130 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
131 {
132 std::string run_from, run_to;
133 clear_flags();
134
135 size_t argidx;
136 for (argidx = 1; argidx < args.size(); argidx++)
137 {
138 if (args[argidx] == "-top" && argidx+1 < args.size()) {
139 top_opt = "-top " + args[++argidx];
140 continue;
141 }
142 if (args[argidx] == "-arch" && argidx+1 < args.size()) {
143 arch = args[++argidx];
144 continue;
145 }
146 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
147 edif_file = args[++argidx];
148 continue;
149 }
150 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
151 blif_file = args[++argidx];
152 continue;
153 }
154 if (args[argidx] == "-run" && argidx+1 < args.size()) {
155 size_t pos = args[argidx+1].find(':');
156 if (pos == std::string::npos)
157 break;
158 run_from = args[++argidx].substr(0, pos);
159 run_to = args[argidx].substr(pos+1);
160 continue;
161 }
162 if (args[argidx] == "-flatten") {
163 flatten = true;
164 continue;
165 }
166 if (args[argidx] == "-retime") {
167 retime = true;
168 continue;
169 }
170 if (args[argidx] == "-nocarry") {
171 nocarry = true;
172 continue;
173 }
174 if (args[argidx] == "-nowidelut") {
175 nowidelut = true;
176 continue;
177 }
178 if (args[argidx] == "-vpr") {
179 vpr = true;
180 continue;
181 }
182 if (args[argidx] == "-nocarry") {
183 nocarry = true;
184 continue;
185 }
186 if (args[argidx] == "-nobram") {
187 nobram = true;
188 continue;
189 }
190 if (args[argidx] == "-nodram") {
191 nodram = true;
192 continue;
193 }
194 if (args[argidx] == "-nosrl") {
195 nosrl = true;
196 continue;
197 }
198 if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
199 widemux = atoi(args[++argidx].c_str());
200 continue;
201 }
202 if (args[argidx] == "-abc9") {
203 abc9 = true;
204 continue;
205 }
206 break;
207 }
208 extra_args(args, argidx, design);
209
210 if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
211 log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
212
213 if (widemux != 0 && widemux < 5)
214 log_cmd_error("-widemux value must be 0 or >= 5.\n");
215
216 if (!design->full_selection())
217 log_cmd_error("This command only operates on fully selected designs!\n");
218
219 log_header(design, "Executing SYNTH_XILINX pass.\n");
220 log_push();
221
222 run_script(design, run_from, run_to);
223
224 log_pop();
225 }
226
227 void script() YS_OVERRIDE
228 {
229 if (check_label("begin")) {
230 if (vpr)
231 run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
232 else
233 run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
234
235 run("read_verilog -lib +/xilinx/cells_xtra.v");
236
237 if (!nobram || help_mode)
238 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
239
240 run(stringf("hierarchy -check %s", top_opt.c_str()));
241 }
242
243 if (check_label("coarse")) {
244 run("proc");
245 if (flatten || help_mode)
246 run("flatten", "(with -flatten only)");
247 run("opt_expr");
248 run("opt_clean");
249 run("check");
250 run("opt");
251 if (help_mode)
252 run("wreduce [c:* t:$mux %d]", "(selection for '-widemux' only)");
253 else
254 run("wreduce" + std::string(widemux > 0 ? " c:* t:$mux %d" : ""));
255 run("peepopt");
256 run("opt_clean");
257 run("alumacc");
258 run("share");
259 run("opt");
260 run("fsm");
261 run("opt -fast");
262 run("memory -nomap");
263 run("opt_clean");
264
265 if (widemux > 0 || help_mode)
266 run("muxpack", " ('-widemux' only)");
267
268 // shregmap -tech xilinx can cope with $shiftx and $mux
269 // cells for identifying variable-length shift registers,
270 // so attempt to convert $pmux-es to the former
271 // Also: wide multiplexer inference benefits from this too
272 if (!(nosrl && widemux == 0) || help_mode)
273 run("pmux2shiftx", "(skip if '-nosrl' and '-widemux' < 5)");
274 }
275
276 if (check_label("bram", "(skip if '-nobram')")) {
277 if (!nobram || help_mode) {
278 run("memory_bram -rules +/xilinx/brams.txt");
279 run("techmap -map +/xilinx/brams_map.v");
280 }
281 }
282
283 if (check_label("dram", "(skip if '-nodram')")) {
284 if (!nodram || help_mode) {
285 run("memory_bram -rules +/xilinx/drams.txt");
286 run("techmap -map +/xilinx/drams_map.v");
287 }
288 }
289
290 if (check_label("fine")) {
291 run("opt -fast -full");
292 run("memory_map");
293 run("dffsr2dff");
294 run("dff2dffe");
295 if (widemux > 0 || help_mode) {
296 run("simplemap t:$mux", " ('-widemux' only)");
297 if (widemux > 0 || help_mode) {
298 std::string muxcover_args = " -dmux=0";
299 switch (widemux) {
300 // NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
301 // of those so that 4:1 muxes and below are implemented
302 // out of mux2s
303 case 5: muxcover_args += " -mux8=350 -mux16=400"; break;
304 case 6: muxcover_args += " -mux8=450 -mux16=500"; break;
305 case 7: muxcover_args += " -mux8=550 -mux16=600"; break;
306 case 8: muxcover_args += " -mux8=650 -mux16=700"; break;
307 case 9: muxcover_args += " -mux16=750"; break;
308 case 10: muxcover_args += " -mux16=850"; break;
309 case 11: muxcover_args += " -mux16=950"; break;
310 case 12: muxcover_args += " -mux16=1050"; break;
311 case 13: muxcover_args += " -mux16=1150"; break;
312 case 14: muxcover_args += " -mux16=1250"; break;
313 case 15: muxcover_args += " -mux16=1350"; break;
314 default: muxcover_args += " -mux16=1450"; break;
315 }
316 run("muxcover " + muxcover_args, "('-widemux' only)");
317 }
318 }
319 run("opt -full");
320
321 if (!nosrl || help_mode) {
322 // shregmap operates on bit-level flops, not word-level,
323 // so break those down here
324 run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
325 // shregmap with '-tech xilinx' infers variable length shift regs
326 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
327 }
328
329 std::string techmap_args = " -map +/techmap.v";
330 if (help_mode)
331 techmap_args += " [-map +/xilinx/mux_map.v]";
332 else if (widemux > 0)
333 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
334 if (help_mode)
335 techmap_args += " [-map +/xilinx/arith_map.v]";
336 else if (!nocarry) {
337 techmap_args += " -map +/xilinx/arith_map.v";
338 if (vpr)
339 techmap_args += " -D _EXPLICIT_CARRY";
340 else if (abc9)
341 techmap_args += " -D _CLB_CARRY";
342 }
343 run("techmap " + techmap_args);
344 run("opt -fast");
345 }
346
347 if (check_label("map_cells")) {
348 std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
349 if (widemux > 0)
350 techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
351 run("techmap " + techmap_args);
352 run("clean");
353 }
354
355 if (check_label("map_luts")) {
356 run("opt_expr -mux_undef");
357 if (help_mode)
358 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
359 else if (abc9) {
360 if (nowidelut)
361 run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
362 else
363 run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
364 }
365 else {
366 if (nowidelut)
367 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
368 else
369 run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
370 }
371 run("clean");
372
373 // This shregmap call infers fixed length shift registers after abc
374 // has performed any necessary retiming
375 if (!nosrl || help_mode)
376 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
377 run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
378 run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
379 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
380 run("clean");
381 }
382
383 if (check_label("check")) {
384 run("hierarchy -check");
385 run("stat -tech xilinx");
386 run("check -noinit");
387 }
388
389 if (check_label("edif")) {
390 if (!edif_file.empty() || help_mode)
391 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
392 }
393
394 if (check_label("blif")) {
395 if (!blif_file.empty() || help_mode)
396 run(stringf("write_blif %s", edif_file.c_str()));
397 }
398 }
399 } SynthXilinxPass;
400
401 PRIVATE_NAMESPACE_END