techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 #define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
  29                              // to one LUT6 (instead of a LUT5 + LUT2)
  30
  31 struct SynthXilinxPass : public ScriptPass
  32 {
  33         SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  34
  35         void help() YS_OVERRIDE
  36         {
  37                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  38                 log("\n");
  39                 log("    synth_xilinx [options]\n");
  40                 log("\n");
  41                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  42                 log("partly selected designs. At the moment this command creates netlists that are\n");
  43                 log("compatible with 7-Series Xilinx devices.\n");
  44                 log("\n");
  45                 log("    -top <module>\n");
  46                 log("        use the specified module as top module\n");
  47                 log("\n");
  48                 log("    -arch {xcup|xcu|xc7|xc6s}\n");
  49                 log("        run synthesis for the specified Xilinx architecture\n");
  50                 log("        default: xc7\n");
  51                 log("\n");
  52                 log("    -edif <file>\n");
  53                 log("        write the design to the specified edif file. writing of an output file\n");
  54                 log("        is omitted if this parameter is not specified.\n");
  55                 log("\n");
  56                 log("    -blif <file>\n");
  57                 log("        write the design to the specified BLIF file. writing of an output file\n");
  58                 log("        is omitted if this parameter is not specified.\n");
  59                 log("\n");
  60                 log("    -vpr\n");
  61                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  62                 log("        (this feature is experimental and incomplete)\n");
  63                 log("\n");
  64                 log("    -nocarry\n");
  65                 log("        disable inference of carry chains\n");
  66                 log("\n");
  67                 log("    -nobram\n");
  68                 log("        disable inference of block rams\n");
  69                 log("\n");
  70                 log("    -nodram\n");
  71                 log("        disable inference of distributed rams\n");
  72                 log("\n");
  73                 log("    -nosrl\n");
  74                 log("        disable inference of shift registers\n");
  75                 log("\n");
  76                 log("    -nocarry\n");
  77                 log("        do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
  78                 log("\n");
  79                 log("    -nowidelut\n");
  80                 log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
  81                 log("\n");
  82                 log("    -run <from_label>:<to_label>\n");
  83                 log("        only run the commands between the labels (see below). an empty\n");
  84                 log("        from label is synonymous to 'begin', and empty to label is\n");
  85                 log("        synonymous to the end of the command list.\n");
  86                 log("\n");
  87                 log("    -flatten\n");
  88                 log("        flatten design before synthesis\n");
  89                 log("\n");
  90                 log("    -retime\n");
  91                 log("        run 'abc' with -dff option\n");
  92                 log("\n");
  93                 log("    -abc9\n");
  94                 log("        use new ABC9 flow (EXPERIMENTAL)\n");
  95                 log("\n");
  96                 log("\n");
  97                 log("The following commands are executed by this synthesis command:\n");
  98                 help_script();
  99                 log("\n");
 100         }
 101
 102         std::string top_opt, edif_file, blif_file, abc, arch;
 103         bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
 104
 105         void clear_flags() YS_OVERRIDE
 106         {
 107                 top_opt = "-auto-top";
 108                 edif_file.clear();
 109                 blif_file.clear();
 110                 arch = "xc7";
 111                 flatten = false;
 112                 retime = false;
 113                 vpr = false;
 114                 nocarry = false;
 115                 nobram = false;
 116                 nodram = false;
 117                 nosrl = false;
 118                 nocarry = false;
 119                 nowidelut = false;
 120                 abc9 = false;
 121         }
 122
 123         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 124         {
 125                 std::string run_from, run_to;
 126                 clear_flags();
 127
 128                 size_t argidx;
 129                 for (argidx = 1; argidx < args.size(); argidx++)
 130                 {
 131                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 132                                 top_opt = "-top " + args[++argidx];
 133                                 continue;
 134                         }
 135                         if (args[argidx] == "-arch" && argidx+1 < args.size()) {
 136                                 arch = args[++argidx];
 137                                 continue;
 138                         }
 139                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 140                                 edif_file = args[++argidx];
 141                                 continue;
 142                         }
 143                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 144                                 blif_file = args[++argidx];
 145                                 continue;
 146                         }
 147                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 148                                 size_t pos = args[argidx+1].find(':');
 149                                 if (pos == std::string::npos)
 150                                         break;
 151                                 run_from = args[++argidx].substr(0, pos);
 152                                 run_to = args[argidx].substr(pos+1);
 153                                 continue;
 154                         }
 155                         if (args[argidx] == "-flatten") {
 156                                 flatten = true;
 157                                 continue;
 158                         }
 159                         if (args[argidx] == "-retime") {
 160                                 retime = true;
 161                                 continue;
 162                         }
 163                         if (args[argidx] == "-nocarry") {
 164                                 nocarry = true;
 165                                 continue;
 166                         }
 167                         if (args[argidx] == "-nowidelut") {
 168                                 nowidelut = true;
 169                                 continue;
 170                         }
 171                         if (args[argidx] == "-vpr") {
 172                                 vpr = true;
 173                                 continue;
 174                         }
 175                         if (args[argidx] == "-nocarry") {
 176                                 nocarry = true;
 177                                 continue;
 178                         }
 179                         if (args[argidx] == "-nobram") {
 180                                 nobram = true;
 181                                 continue;
 182                         }
 183                         if (args[argidx] == "-nodram") {
 184                                 nodram = true;
 185                                 continue;
 186                         }
 187                         if (args[argidx] == "-nosrl") {
 188                                 nosrl = true;
 189                                 continue;
 190                         }
 191                         if (args[argidx] == "-abc9") {
 192                                 abc9 = true;
 193                                 continue;
 194                         }
 195                         break;
 196                 }
 197                 extra_args(args, argidx, design);
 198
 199                 if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
 200                         log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
 201
 202                 if (!design->full_selection())
 203                         log_cmd_error("This command only operates on fully selected designs!\n");
 204
 205                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 206                 log_push();
 207
 208                 run_script(design, run_from, run_to);
 209
 210                 log_pop();
 211         }
 212
 213         void script() YS_OVERRIDE
 214         {
 215                 if (check_label("begin")) {
 216                         if (vpr)
 217                                 run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 218                         else
 219                                 run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 220
 221                         run("read_verilog -lib +/xilinx/cells_xtra.v");
 222
 223                         if (!nobram || help_mode)
 224                                 run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
 225
 226                         run(stringf("hierarchy -check %s", top_opt.c_str()));
 227                 }
 228
 229                 if (check_label("flatten", "(with '-flatten' only)")) {
 230                         if (flatten || help_mode) {
 231                                 run("proc");
 232                                 run("flatten");
 233                         }
 234                 }
 235
 236                 if (check_label("coarse")) {
 237                         run("synth -run coarse");
 238
 239                         // shregmap -tech xilinx can cope with $shiftx and $mux
 240                         //   cells for identifying variable-length shift registers,
 241                         //   so attempt to convert $pmux-es to the former
 242                         if (!nosrl || help_mode)
 243                                 run("pmux2shiftx", "(skip if '-nosrl')");
 244
 245                         // Run a number of peephole optimisations, including one
 246                         //   that optimises $mul cells driving $shiftx's B input
 247                         //   and that aids wide mux analysis
 248                         run("peepopt");
 249                 }
 250
 251                 if (check_label("bram", "(skip if '-nobram')")) {
 252                         if (!nobram || help_mode) {
 253                                 run("memory_bram -rules +/xilinx/brams.txt");
 254                                 run("techmap -map +/xilinx/brams_map.v");
 255                         }
 256                 }
 257
 258                 if (check_label("dram", "(skip if '-nodram')")) {
 259                         if (!nodram || help_mode) {
 260                                 run("memory_bram -rules +/xilinx/drams.txt");
 261                                 run("techmap -map +/xilinx/drams_map.v");
 262                         }
 263                 }
 264
 265                 if (check_label("fine")) {
 266                         run("opt -fast -full");
 267                         run("memory_map");
 268                         run("dffsr2dff");
 269                         run("dff2dffe");
 270                         run("opt -full");
 271
 272                         if (!nosrl || help_mode) {
 273                                 // shregmap operates on bit-level flops, not word-level,
 274                                 //   so break those down here
 275                                 run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 276                                 // shregmap with '-tech xilinx' infers variable length shift regs
 277                                 run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 278                         }
 279
 280                         std::string techmap_files = " -map +/techmap.v";
 281                         if (help_mode)
 282                                 techmap_files += " [-map +/xilinx/arith_map.v]";
 283                         else if (!nocarry) {
 284                                 techmap_files += " -map +/xilinx/arith_map.v";
 285                                 if (vpr)
 286                                         techmap_files += " -D _EXPLICIT_CARRY";
 287                                 else if (abc9)
 288                                         techmap_files += " -D _CLB_CARRY";
 289                         }
 290                         run("techmap " + techmap_files);
 291                         run("opt -fast");
 292                 }
 293
 294                 if (check_label("map_cells")) {
 295                         run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 296                         run("clean");
 297                 }
 298
 299                 if (check_label("map_luts")) {
 300                         run("opt_expr -mux_undef");
 301                         if (help_mode)
 302                                 run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
 303                         else if (abc9) {
 304                                 if (nowidelut)
 305                                         run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 306                                 else
 307                                         run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
 308                         }
 309                         else {
 310                                 if (nowidelut)
 311                                         run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 312                                 else
 313                                         run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 314                         }
 315                         run("clean");
 316
 317                         // This shregmap call infers fixed length shift registers after abc
 318                         //   has performed any necessary retiming
 319                         if (!nosrl || help_mode)
 320                                 run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 321                         run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 322                         run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 323                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 324                         run("clean");
 325                 }
 326
 327                 if (check_label("check")) {
 328                         run("hierarchy -check");
 329                         run("stat -tech xilinx");
 330                         run("check -noinit");
 331                 }
 332
 333                 if (check_label("edif")) {
 334                         if (!edif_file.empty() || help_mode)
 335                                 run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
 336                 }
 337
 338                 if (check_label("blif")) {
 339                         if (!blif_file.empty() || help_mode)
 340                                 run(stringf("write_blif %s", edif_file.c_str()));
 341                 }
 342         }
 343 } SynthXilinxPass;
 344
 345 PRIVATE_NAMESPACE_END