2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
30 if (label
== run_from
)
37 struct SynthXilinxPass
: public Pass
39 SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
41 void help() YS_OVERRIDE
43 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
45 log(" synth_xilinx [options]\n");
47 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
48 log("partly selected designs. At the moment this command creates netlists that are\n");
49 log("compatible with 7-Series Xilinx devices.\n");
51 log(" -top <module>\n");
52 log(" use the specified module as top module\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
58 log(" -blif <file>\n");
59 log(" write the design to the specified BLIF file. writing of an output file\n");
60 log(" is omitted if this parameter is not specified.\n");
63 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
64 log(" (this feature is experimental and incomplete)\n");
67 log(" disable inference of block rams\n");
70 log(" disable inference of distributed rams\n");
73 log(" disable inference of shift registers\n");
76 log(" do not use XORCY/MUXCY cells in output netlist\n");
79 log(" do not use MUXF[78] muxes to implement LUTs larger than LUT6s\n");
81 log(" -run <from_label>:<to_label>\n");
82 log(" only run the commands between the labels (see below). an empty\n");
83 log(" from label is synonymous to 'begin', and empty to label is\n");
84 log(" synonymous to the end of the command list.\n");
87 log(" flatten design before synthesis\n");
90 log(" run 'abc' with -dff option\n");
93 log("The following commands are executed by this synthesis command:\n");
96 log(" read_verilog -lib +/xilinx/cells_sim.v\n");
97 log(" read_verilog -lib +/xilinx/cells_xtra.v\n");
98 log(" read_verilog -lib +/xilinx/brams_bb.v\n");
99 log(" hierarchy -check -top <top>\n");
101 log(" flatten: (only if -flatten)\n");
106 log(" synth -run coarse\n");
108 log(" bram: (only executed when '-nobram' is not given)\n");
109 log(" memory_bram -rules +/xilinx/brams.txt\n");
110 log(" techmap -map +/xilinx/brams_map.v\n");
112 log(" dram: (only executed when '-nodram' is not given)\n");
113 log(" memory_bram -rules +/xilinx/drams.txt\n");
114 log(" techmap -map +/xilinx/drams_map.v\n");
118 log(" memory_map\n");
121 log(" techmap -map +/xilinx/arith_map.v\n");
124 log(" map_cells:\n");
125 log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
126 log(" pmux2shiftx (without '-nosrl' only)\n");
127 log(" opt_expr -mux_undef (without '-nosrl' only)\n");
128 log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
129 log(" techmap -map +/xilinx/cells_map.v\n");
134 log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
135 log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
137 log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
138 log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
139 log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
140 log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
144 log(" hierarchy -check\n");
146 log(" check -noinit\n");
148 log(" edif: (only if -edif)\n");
149 log(" write_edif <file-name>\n");
151 log(" blif: (only if -blif)\n");
152 log(" write_blif <file-name>\n");
155 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
157 std::string top_opt
= "-auto-top";
158 std::string edif_file
;
159 std::string blif_file
;
160 std::string run_from
, run_to
;
161 bool flatten
= false;
163 bool nocarry
= false;
171 for (argidx
= 1; argidx
< args
.size(); argidx
++)
173 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
174 top_opt
= "-top " + args
[++argidx
];
177 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
178 edif_file
= args
[++argidx
];
181 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
182 blif_file
= args
[++argidx
];
185 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
186 size_t pos
= args
[argidx
+1].find(':');
187 if (pos
== std::string::npos
)
189 run_from
= args
[++argidx
].substr(0, pos
);
190 run_to
= args
[argidx
].substr(pos
+1);
193 if (args
[argidx
] == "-flatten") {
197 if (args
[argidx
] == "-retime") {
201 if (args
[argidx
] == "-nocarry") {
205 if (args
[argidx
] == "-nomux") {
209 if (args
[argidx
] == "-vpr") {
213 if (args
[argidx
] == "-nobram") {
217 if (args
[argidx
] == "-nodram") {
221 if (args
[argidx
] == "-nosrl") {
227 extra_args(args
, argidx
, design
);
229 if (!design
->full_selection())
230 log_cmd_error("This command only operates on fully selected designs!\n");
232 bool active
= run_from
.empty();
234 log_header(design
, "Executing SYNTH_XILINX pass.\n");
237 if (check_label(active
, run_from
, run_to
, "begin"))
240 Pass::call(design
, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
242 Pass::call(design
, "read_verilog -lib +/xilinx/cells_sim.v");
245 Pass::call(design
, "read_verilog -lib +/xilinx/cells_xtra.v");
248 Pass::call(design
, "read_verilog -lib +/xilinx/brams_bb.v");
251 Pass::call(design
, stringf("hierarchy -check %s", top_opt
.c_str()));
254 if (flatten
&& check_label(active
, run_from
, run_to
, "flatten"))
256 Pass::call(design
, "proc");
257 Pass::call(design
, "flatten");
260 if (check_label(active
, run_from
, run_to
, "coarse"))
262 Pass::call(design
, "synth -run coarse");
265 if (check_label(active
, run_from
, run_to
, "bram"))
268 Pass::call(design
, "memory_bram -rules +/xilinx/brams.txt");
269 Pass::call(design
, "techmap -map +/xilinx/brams_map.v");
273 if (check_label(active
, run_from
, run_to
, "dram"))
276 Pass::call(design
, "memory_bram -rules +/xilinx/drams.txt");
277 Pass::call(design
, "techmap -map +/xilinx/drams_map.v");
281 if (check_label(active
, run_from
, run_to
, "fine"))
283 Pass::call(design
, "opt -fast");
284 Pass::call(design
, "memory_map");
285 Pass::call(design
, "dffsr2dff");
286 Pass::call(design
, "dff2dffe");
289 Pass::call(design
, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
291 Pass::call(design
, "techmap -map +/xilinx/arith_map.v");
294 Pass::call(design
, "opt -fast");
297 if (check_label(active
, run_from
, run_to
, "map_cells"))
300 // shregmap operates on bit-level flops, not word-level,
301 // so break those down here
302 Pass::call(design
, "simplemap t:$dff t:$dffe");
303 // shregmap -tech xilinx can cope with $shiftx and $mux
304 // cells for identifiying variable-length shift registers,
305 // so attempt to convert $pmux-es to the former
306 Pass::call(design
, "pmux2shiftx");
307 // pmux2shiftx can leave behind a $pmux with a single entry
308 // -- need this to clean that up before shregmap
309 Pass::call(design
, "opt_expr -mux_undef");
310 // shregmap with '-tech xilinx' infers variable length shift regs
311 Pass::call(design
, "shregmap -tech xilinx -minlen 3");
314 Pass::call(design
, "techmap -map +/xilinx/cells_map.v");
315 Pass::call(design
, "clean");
318 if (check_label(active
, run_from
, run_to
, "map_luts"))
320 Pass::call(design
, "opt -full");
321 Pass::call(design
, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
323 Pass::call(design
, "abc -luts 2:2,3,6:5" + string(retime
? " -dff" : ""));
325 Pass::call(design
, "abc -luts 2:2,3,6:5,10,20" + string(retime
? " -dff" : ""));
326 Pass::call(design
, "clean");
327 // This shregmap call infers fixed length shift registers after abc
328 // has performed any necessary retiming
330 Pass::call(design
, "shregmap -minlen 3 -init -params -enpol any_or_none");
331 Pass::call(design
, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
332 Pass::call(design
, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
333 "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
334 Pass::call(design
, "clean");
337 if (check_label(active
, run_from
, run_to
, "check"))
339 Pass::call(design
, "hierarchy -check");
340 Pass::call(design
, "stat");
341 Pass::call(design
, "check -noinit");
344 if (check_label(active
, run_from
, run_to
, "edif"))
346 if (!edif_file
.empty())
347 Pass::call(design
, stringf("write_edif -pvector bra %s", edif_file
.c_str()));
349 if (check_label(active
, run_from
, run_to
, "blif"))
351 if (!blif_file
.empty())
352 Pass::call(design
, stringf("write_blif %s", edif_file
.c_str()));
359 PRIVATE_NAMESPACE_END