techlibs/xilinx/synth_xilinx.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
  29 {
  30         if (label == run_from)
  31                 active = true;
  32         if (label == run_to)
  33                 active = false;
  34         return active;
  35 }
  36
  37 struct SynthXilinxPass : public Pass
  38 {
  39         SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
  40
  41         void help() YS_OVERRIDE
  42         {
  43                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  44                 log("\n");
  45                 log("    synth_xilinx [options]\n");
  46                 log("\n");
  47                 log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
  48                 log("partly selected designs. At the moment this command creates netlists that are\n");
  49                 log("compatible with 7-Series Xilinx devices.\n");
  50                 log("\n");
  51                 log("    -top <module>\n");
  52                 log("        use the specified module as top module\n");
  53                 log("\n");
  54                 log("    -edif <file>\n");
  55                 log("        write the design to the specified edif file. writing of an output file\n");
  56                 log("        is omitted if this parameter is not specified.\n");
  57                 log("\n");
  58                 log("    -blif <file>\n");
  59                 log("        write the design to the specified BLIF file. writing of an output file\n");
  60                 log("        is omitted if this parameter is not specified.\n");
  61                 log("\n");
  62                 log("    -vpr\n");
  63                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  64                 log("        (this feature is experimental and incomplete)\n");
  65                 log("\n");
  66                 log("    -nobram\n");
  67                 log("        disable inference of block rams\n");
  68                 log("\n");
  69                 log("    -nodram\n");
  70                 log("        disable inference of distributed rams\n");
  71                 log("\n");
  72                 log("    -nosrl\n");
  73                 log("        disable inference of shift registers\n");
  74                 log("\n");
  75                 log("    -nocarry\n");
  76                 log("        do not use XORCY/MUXCY cells in output netlist\n");
  77                 log("\n");
  78                 log("    -nomux\n");
  79                 log("        do not use MUXF[78] muxes to implement LUTs larger than LUT6s\n");
  80                 log("\n");
  81                 log("    -run <from_label>:<to_label>\n");
  82                 log("        only run the commands between the labels (see below). an empty\n");
  83                 log("        from label is synonymous to 'begin', and empty to label is\n");
  84                 log("        synonymous to the end of the command list.\n");
  85                 log("\n");
  86                 log("    -flatten\n");
  87                 log("        flatten design before synthesis\n");
  88                 log("\n");
  89                 log("    -retime\n");
  90                 log("        run 'abc' with -dff option\n");
  91                 log("\n");
  92                 log("\n");
  93                 log("The following commands are executed by this synthesis command:\n");
  94                 log("\n");
  95                 log("    begin:\n");
  96                 log("        read_verilog -lib +/xilinx/cells_sim.v\n");
  97                 log("        read_verilog -lib +/xilinx/cells_xtra.v\n");
  98                 log("        read_verilog -lib +/xilinx/brams_bb.v\n");
  99                 log("        hierarchy -check -top <top>\n");
 100                 log("\n");
 101                 log("    flatten:     (only if -flatten)\n");
 102                 log("        proc\n");
 103                 log("        flatten\n");
 104                 log("\n");
 105                 log("    coarse:\n");
 106                 log("        synth -run coarse\n");
 107                 log("\n");
 108                 log("    bram: (only executed when '-nobram' is not given)\n");
 109                 log("        memory_bram -rules +/xilinx/brams.txt\n");
 110                 log("        techmap -map +/xilinx/brams_map.v\n");
 111                 log("\n");
 112                 log("    dram: (only executed when '-nodram' is not given)\n");
 113                 log("        memory_bram -rules +/xilinx/drams.txt\n");
 114                 log("        techmap -map +/xilinx/drams_map.v\n");
 115                 log("\n");
 116                 log("    fine:\n");
 117                 log("        opt -fast\n");
 118                 log("        memory_map\n");
 119                 log("        dffsr2dff\n");
 120                 log("        dff2dffe\n");
 121                 log("        techmap -map +/xilinx/arith_map.v\n");
 122                 log("        opt -fast\n");
 123                 log("\n");
 124                 log("    map_cells:\n");
 125                 log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
 126                 log("        pmux2shiftx (without '-nosrl' only)\n");
 127                 log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 128                 log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
 129                 log("        techmap -map +/xilinx/cells_map.v\n");
 130                 log("        clean\n");
 131                 log("\n");
 132                 log("    map_luts:\n");
 133                 log("        opt -full\n");
 134                 log("        techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
 135                 log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 136                 log("        clean\n");
 137                 log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
 138                 log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 139                 log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
 140                 log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 141                 log("        clean\n");
 142                 log("\n");
 143                 log("    check:\n");
 144                 log("        hierarchy -check\n");
 145                 log("        stat\n");
 146                 log("        check -noinit\n");
 147                 log("\n");
 148                 log("    edif:     (only if -edif)\n");
 149                 log("        write_edif <file-name>\n");
 150                 log("\n");
 151                 log("    blif:     (only if -blif)\n");
 152                 log("        write_blif <file-name>\n");
 153                 log("\n");
 154         }
 155         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 156         {
 157                 std::string top_opt = "-auto-top";
 158                 std::string edif_file;
 159                 std::string blif_file;
 160                 std::string run_from, run_to;
 161                 bool flatten = false;
 162                 bool retime = false;
 163                 bool nocarry = false;
 164                 bool nomux = false;
 165                 bool vpr = false;
 166                 bool nobram = false;
 167                 bool nodram = false;
 168                 bool nosrl = false;
 169
 170                 size_t argidx;
 171                 for (argidx = 1; argidx < args.size(); argidx++)
 172                 {
 173                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 174                                 top_opt = "-top " + args[++argidx];
 175                                 continue;
 176                         }
 177                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 178                                 edif_file = args[++argidx];
 179                                 continue;
 180                         }
 181                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 182                                 blif_file = args[++argidx];
 183                                 continue;
 184                         }
 185                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 186                                 size_t pos = args[argidx+1].find(':');
 187                                 if (pos == std::string::npos)
 188                                         break;
 189                                 run_from = args[++argidx].substr(0, pos);
 190                                 run_to = args[argidx].substr(pos+1);
 191                                 continue;
 192                         }
 193                         if (args[argidx] == "-flatten") {
 194                                 flatten = true;
 195                                 continue;
 196                         }
 197                         if (args[argidx] == "-retime") {
 198                                 retime = true;
 199                                 continue;
 200                         }
 201                         if (args[argidx] == "-nocarry") {
 202                                 nocarry = true;
 203                                 continue;
 204                         }
 205                         if (args[argidx] == "-nomux") {
 206                                 nomux = true;
 207                                 continue;
 208                         }
 209                         if (args[argidx] == "-vpr") {
 210                                 vpr = true;
 211                                 continue;
 212                         }
 213                         if (args[argidx] == "-nobram") {
 214                                 nobram = true;
 215                                 continue;
 216                         }
 217                         if (args[argidx] == "-nodram") {
 218                                 nodram = true;
 219                                 continue;
 220                         }
 221                         if (args[argidx] == "-nosrl") {
 222                                 nosrl = true;
 223                                 continue;
 224                         }
 225                         break;
 226                 }
 227                 extra_args(args, argidx, design);
 228
 229                 if (!design->full_selection())
 230                         log_cmd_error("This command only operates on fully selected designs!\n");
 231
 232                 bool active = run_from.empty();
 233
 234                 log_header(design, "Executing SYNTH_XILINX pass.\n");
 235                 log_push();
 236
 237                 if (check_label(active, run_from, run_to, "begin"))
 238                 {
 239                         if (vpr) {
 240                                 Pass::call(design, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 241                         } else {
 242                                 Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
 243                         }
 244
 245                         Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 246
 247                         if (!nobram) {
 248                                 Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
 249                         }
 250
 251                         Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 252                 }
 253
 254                 if (flatten && check_label(active, run_from, run_to, "flatten"))
 255                 {
 256                         Pass::call(design, "proc");
 257                         Pass::call(design, "flatten");
 258                 }
 259
 260                 if (check_label(active, run_from, run_to, "coarse"))
 261                 {
 262                         Pass::call(design, "synth -run coarse");
 263                 }
 264
 265                 if (check_label(active, run_from, run_to, "bram"))
 266                 {
 267                         if (!nobram) {
 268                                 Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
 269                                 Pass::call(design, "techmap -map +/xilinx/brams_map.v");
 270                         }
 271                 }
 272
 273                 if (check_label(active, run_from, run_to, "dram"))
 274                 {
 275                         if (!nodram) {
 276                                 Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
 277                                 Pass::call(design, "techmap -map +/xilinx/drams_map.v");
 278                         }
 279                 }
 280
 281                 if (check_label(active, run_from, run_to, "fine"))
 282                 {
 283                         Pass::call(design, "opt -fast");
 284                         Pass::call(design, "memory_map");
 285                         Pass::call(design, "dffsr2dff");
 286                         Pass::call(design, "dff2dffe");
 287                         if (!nocarry) {
 288                                 if (vpr) {
 289                                         Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
 290                                 } else {
 291                                         Pass::call(design, "techmap -map +/xilinx/arith_map.v");
 292                                 }
 293                         }
 294                         Pass::call(design, "opt -fast");
 295                 }
 296
 297                 if (check_label(active, run_from, run_to, "map_cells"))
 298                 {
 299                         if (!nosrl) {
 300                                 // shregmap operates on bit-level flops, not word-level,
 301                                 //   so break those down here
 302                                 Pass::call(design, "simplemap t:$dff t:$dffe");
 303                                 // shregmap -tech xilinx can cope with $shiftx and $mux
 304                                 //   cells for identifiying variable-length shift registers,
 305                                 //   so attempt to convert $pmux-es to the former
 306                                 Pass::call(design, "pmux2shiftx");
 307                                 // pmux2shiftx can leave behind a $pmux with a single entry
 308                                 //   -- need this to clean that up before shregmap
 309                                 Pass::call(design, "opt_expr -mux_undef");
 310                                 // shregmap with '-tech xilinx' infers variable length shift regs
 311                                 Pass::call(design, "shregmap -tech xilinx -minlen 3");
 312                         }
 313
 314                         Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 315                         Pass::call(design, "clean");
 316                 }
 317
 318                 if (check_label(active, run_from, run_to, "map_luts"))
 319                 {
 320                         Pass::call(design, "opt -full");
 321                         Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
 322                         if (nomux)
 323                                 Pass::call(design, "abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 324                         else
 325                                 Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 326                         Pass::call(design, "clean");
 327                         // This shregmap call infers fixed length shift registers after abc
 328                         //   has performed any necessary retiming
 329                         if (!nosrl)
 330                                 Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
 331                         Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 332                         Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 333                                         "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 334                         Pass::call(design, "clean");
 335                 }
 336
 337                 if (check_label(active, run_from, run_to, "check"))
 338                 {
 339                         Pass::call(design, "hierarchy -check");
 340                         Pass::call(design, "stat");
 341                         Pass::call(design, "check -noinit");
 342                 }
 343
 344                 if (check_label(active, run_from, run_to, "edif"))
 345                 {
 346                         if (!edif_file.empty())
 347                                 Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
 348                 }
 349                 if (check_label(active, run_from, run_to, "blif"))
 350                 {
 351                         if (!blif_file.empty())
 352                                 Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
 353                 }
 354
 355                 log_pop();
 356         }
 357 } SynthXilinxPass;
 358
 359 PRIVATE_NAMESPACE_END